iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

i.MX arm32 device tree change for 5.10:

Browse Source 
- New board/device support: Tolino Shine 2 HD, TQMa6 SoM, Y Soft IOTA
   Orion board.
 - update GPMI NAND node name to nand-controller for aligning with DT
   schema.
 - Remove the legacy fsl,spi-num-chipselects property from a few board.
 - A series to update imx6q-logicpd support, using GPIO chipselect,
   adding board compatible string, and enabling DTB build for the board.
 - Complete RNG device node in i.MX6SL device tree, and add RNG node for
   i.MX6SLL and i.MX6ULL.
 - Correct interrupt flags for imx6qdl-gw5xxx boards.
 - Add missing enet_out clock for i.MX6Q/DL Ethernet device.
 - Enable PCIe support for imx6qp-sabreauto board.
 - A series from Shengjiu Wang to add audio sound card for imx7d-sdb and
   imx6sll-evk board, add headphone detection for sound card on a few NXP
   development boards.
 - A couple of minor fix-ups on i.MX25 pin functions.
 - Some random update on various boards.
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl9qrwoUHHNoYXduZ3Vv
 QGtlcm5lbC5vcmcACgkQUFdYWoewfM7Fqgf/Y+6XGsUY+QHRK6CTglOsDgC43Ixw
 mhJkvG7AWcu+2Oz+WLFVbncbcBBy1swrAAss0DlwAB3BXijWiytSz6flPCBHrFiN
 pyM1CLhgQChI2JfWRRc1ij/WOHkztnxR7CHLOycdhn8WQLFLQeC6Axox+d22IW4L
 NgbR08eq2g2+QjMjHPyGpxnCw7AoGzexCwCLC8ajKTFe16k61bkz5Q2SxXogdlkO
 cusfGpdFDme04Fl/T9sWOyIO/+l1qOzDx5JIQHRVnTB8hY7Dl7r7NQYdcvcdYrIj
 AR31fXEjioR5C+AYr25ZILowZlS8VyvfTi1ZFHMFG3yD+856AYqCDB40Jw==
 =w/3X
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm32 device tree change for 5.10:

- New board/device support: Tolino Shine 2 HD, TQMa6 SoM, Y Soft IOTA
  Orion board.
- update GPMI NAND node name to nand-controller for aligning with DT
  schema.
- Remove the legacy fsl,spi-num-chipselects property from a few board.
- A series to update imx6q-logicpd support, using GPIO chipselect,
  adding board compatible string, and enabling DTB build for the board.
- Complete RNG device node in i.MX6SL device tree, and add RNG node for
  i.MX6SLL and i.MX6ULL.
- Correct interrupt flags for imx6qdl-gw5xxx boards.
- Add missing enet_out clock for i.MX6Q/DL Ethernet device.
- Enable PCIe support for imx6qp-sabreauto board.
- A series from Shengjiu Wang to add audio sound card for imx7d-sdb and
  imx6sll-evk board, add headphone detection for sound card on a few NXP
  development boards.
- A couple of minor fix-ups on i.MX25 pin functions.
- Some random update on various boards.

* tag 'imx-dt-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (37 commits)
  ARM: dts: imx6qdl-gw5xxx: correct interrupt flags
  ARM: dts: imx6q-logicpd: Use GPIO chipselect
  ARM: dts: imx: Add an entry for imx6q-logicpd.dtb
  ARM: dts: imx6q-logicpd: Add a specific board compatible string
  ARM: dts: imx6q: align GPIO hog names with dtschema
  ARM: dts: imx6qdl-tqma6: fix LM75 compatible string
  ARM: dts: imx6qdl-tqma6: remove obsolete fsl,spi-num-chipselects
  ARM: dts: imx6qdl-tqma6: fix indentation
  ARM: dts: imx28-m28: Align GPMI NAND node name with schema
  ARM: dts: imx6qdl: add enet_out clk support
  ARM: dts: imx6qdl: move iomuxc compatible assignment out of root node
  ARM: dts: vf: Fix PCA95xx GPIO expander properties on ZII CFU1
  ARM: dts: imx: add devicetree for Tolino Shine 2 HD
  ARM: dts: imx6qdl-gw553x: Remove unneeded #address-cells/#size-cells
  ARM: dts: imx6sll-evk: Add audio sound card node
  ARM: dts: imx6sl-evk: Add headphone detection for sound card
  ARM: dts: imx6sx-sdb: Add headphone detection for sound card
  ARM: dts: imx6q-kontron-samx6i: Remove old fsl,spi-num-chipselects
  ARM: dts: imx: Fix the SPI chipselect polarity
  ARM: dts: imx25-pinfunc: Fix GPT function names
  ...

Link: https://lore.kernel.org/r/20200923073009.23678-4-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-09-26 10:17:03 -07:00
commit 2b7cfaaf0b
110 changed files with 1425 additions and 168 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/Makefile
View File

@ -484,6 +484,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-wandboard-revd1.dtb \
imx6dl-yapp4-draco.dtb \
imx6dl-yapp4-hydra.dtb \
imx6dl-yapp4-orion.dtb \
imx6dl-yapp4-ursa.dtb \
imx6q-apalis-eval.dtb \
imx6q-apalis-ixora.dtb \
@ -533,6 +534,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-icore-ofcap12.dtb \
imx6q-icore-rqs.dtb \
imx6q-kp-tpc.dtb \
imx6q-logicpd.dtb \
imx6q-marsboard.dtb \
imx6q-mccmon6.dtb \
imx6q-nitrogen6x.dtb \
@ -587,6 +589,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-zii-rdu2.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-tolino-shine2hd.dtb \
imx6sl-tolino-shine3.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \

2
arch/arm/boot/dts/imx23-evk.dts
View File

@ -53,7 +53,7 @@
apb@80000000 {
apbh@80000000 {
gpmi-nand@8000c000 {
nand-controller@8000c000 {
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>;
status = "okay";

2
arch/arm/boot/dts/imx23.dtsi
View File

@ -76,7 +76,7 @@
status = "disabled";
};
gpmi-nand@8000c000 {
nand-controller@8000c000 {
compatible = "fsl,imx23-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;

28
arch/arm/boot/dts/imx25-pinfunc.h
View File

@ -87,6 +87,7 @@
#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000
#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000
#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000
#define MX25_PAD_EB1__CSPI3_SS1 0x044 0x25c 0x4c0 0x06 0x000
#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000
#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000
@ -112,6 +113,7 @@
#define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000
#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000
#define MX25_PAD_NF_CE0__CSPI1_SS3 0x05c 0x26c 0x490 0x01 0x000
#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000
#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000
@ -122,6 +124,7 @@
#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000
#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000
#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000
#define MX25_PAD_LBA__CSPI3_RDY 0x064 0x274 0x4b0 0x06 0x000
#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000
#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000
@ -285,7 +288,8 @@
#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000
#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000
#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x01 0x000
#define MX25_PAD_CONTRAST__GPT4_CAPIN1 0x118 0x310 0x000 0x01 0x000
#define MX25_PAD_CONTRAST__CSPI2_SS1 0x118 0x310 0x4a8 0x02 0x000
#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000
#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001
#define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000
@ -298,7 +302,7 @@
#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001
#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000
#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000
#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x07 0x000
#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x4b8 0x07 0x001
#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000
#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000
@ -310,23 +314,25 @@
#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001
#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000
#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x07 0x000
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x4ac 0x07 0x001
#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000
#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000
#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000
#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x4b0 0x07 0x001
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000
/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
#define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000
#define MX25_PAD_CSI_D6__CSPI3_SS0 0x130 0x328 0x4bc 0x07 0x001
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000
#define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000
#define MX25_PAD_CSI_D7__CSPI3_SS1 0x134 0x32c 0x4c0 0x07 0x001
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000
#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000
@ -398,7 +404,7 @@
#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000
#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001
#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x02 0x000
#define MX25_PAD_UART1_RTS__GPT3_CAPIN1 0x178 0x370 0x000 0x02 0x000
#define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000
#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000
@ -415,12 +421,14 @@
#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000
#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002
#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000
#define MX25_PAD_UART2_RTS__GPT1_CAPIN1 0x188 0x380 0x000 0x03 0x000
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000
#define MX25_PAD_UART2_RTS__CSPI2_SS3 0x188 0x380 0x000 0x06 0x000
#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000
#define MX25_PAD_UART2_CTS__CSPI3_SS3 0x18c 0x384 0x4c8 0x06 0x001
/*
* Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD
@ -446,14 +454,17 @@
#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000
#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA1__CSPI2_RDY 0x19c 0x394 0x498 0x01 0x001
#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000
#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000
#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA2__CSPI2_SS0 0x1a0 0x398 0x4a4 0x01 0x001
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002
#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000
#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA3__CSPI2_SS1 0x1a4 0x39c 0x4a8 0x01 0x001
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002
#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000
@ -564,11 +575,15 @@
#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000
#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001
#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001
#define MX25_PAD_GPIO_C__GPT2_CAPIN1 0x1fc 0x3f8 0x000 0x04 0x000
#define MX25_PAD_GPIO_C__CSPI1_SS2 0x1fc 0x3f8 0x000 0x05 0x000
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000
#define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000
#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000
#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001
#define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001
#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000
#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002
@ -593,6 +608,7 @@
#define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002
#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000
#define MX25_PAD_VSTBY_ACK__CSPI1_SS3 0x218 0x40c 0x490 0x02 0x001
#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000
#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000

4
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
View File

@ -18,8 +18,8 @@
};
&cspi1 {
cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
<&gpio4 27 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>,
<&gpio4 27 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
View File

@ -65,7 +65,7 @@
&cspi1 {
pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>,
<&gpio4 27 GPIO_ACTIVE_LOW>;
};

2
arch/arm/boot/dts/imx27.dtsi
View File

@ -558,7 +558,7 @@
};
};
nfc: nand@d8000000 {
nfc: nand-controller@d8000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx27-nand";

2
arch/arm/boot/dts/imx28-apf28.dts
View File

@ -17,7 +17,7 @@
apb@80000000 {
apbh@80000000 {
gpmi-nand@8000c000 {
nand-controller@8000c000 {
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
status = "okay";

2
arch/arm/boot/dts/imx28-apx4devkit.dts
View File

@ -13,7 +13,7 @@
apb@80000000 {
apbh@80000000 {
gpmi-nand@8000c000 {
nand-controller@8000c000 {
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
status = "okay";

2
arch/arm/boot/dts/imx28-evk.dts
View File

@ -97,7 +97,7 @@
apb@80000000 {
apbh@80000000 {
gpmi-nand@8000c000 {
nand-controller@8000c000 {
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg
&gpmi_pins_evk>;

2
arch/arm/boot/dts/imx28-m28.dtsi
View File

@ -16,7 +16,7 @@
apb@80000000 {
apbh@80000000 {
gpmi-nand@8000c000 {
nand-controller@8000c000 {
#address-cells = <1>;
#size-cells = <1>;
pinctrl-names = "default";

2
arch/arm/boot/dts/imx28-m28cu3.dts
View File

@ -17,7 +17,7 @@
apb@80000000 {
apbh@80000000 {
gpmi-nand@8000c000 {
nand-controller@8000c000 {
#address-cells = <1>;
#size-cells = <1>;
pinctrl-names = "default";

2
arch/arm/boot/dts/imx28.dtsi
View File

@ -100,7 +100,7 @@
status = "disabled";
};
gpmi: gpmi-nand@8000c000 {
gpmi: nand-controller@8000c000 {
compatible = "fsl,imx28-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm/boot/dts/imx50-evk.dts
View File

@ -20,7 +20,7 @@
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi>;
cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>;
cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>;
status = "okay";
flash: m25p32@1 {

4
arch/arm/boot/dts/imx51-apf51dev.dts
View File

@ -74,8 +74,8 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
<&gpio4 25 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>,
<&gpio4 25 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/boot/dts/imx53-m53menlo.dts
View File

@ -104,7 +104,7 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio2 27 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio2 27 GPIO_ACTIVE_LOW>;
status = "okay";
spidev@0 {

2
arch/arm/boot/dts/imx53-smd.dts
View File

@ -58,7 +58,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
status = "okay";
zigbee: mc1323@0 {

8
arch/arm/boot/dts/imx53-tqma53.dtsi
View File

@ -50,8 +50,8 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
<&gpio3 24 0>, <&gpio3 25 0>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>,
<&gpio3 24 GPIO_ACTIVE_LOW>, <&gpio3 25 GPIO_ACTIVE_LOW>;
status = "disabled";
};
@ -251,8 +251,8 @@
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi>;
cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
<&gpio1 21 0>;
cs-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>, <&gpio1 19 GPIO_ACTIVE_LOW>,
<&gpio1 21 GPIO_ACTIVE_LOW>;
status = "disabled";
};

3
arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
View File

@ -119,7 +119,8 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>,
<&gpio2 16 GPIO_ACTIVE_LOW>, <&gpio2 17 GPIO_ACTIVE_LOW>;
status = "okay";
};

3
arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
View File

@ -212,6 +212,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
status = "disabled";
};
@ -383,7 +384,7 @@
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
>;
};

2
arch/arm/boot/dts/imx6dl-aristainetos_4.dts
View File

@ -61,7 +61,7 @@
};
&ecspi2 {
cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";

4
arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
View File

@ -67,7 +67,7 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
@ -80,7 +80,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@0 {

4
arch/arm/boot/dts/imx6dl-prtrvt.dts
View File

@ -37,7 +37,7 @@
};
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@ -52,7 +52,7 @@
};
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";

2
arch/arm/boot/dts/imx6dl-prtvt7.dts
View File

@ -219,7 +219,7 @@
};
&ecspi2 {
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";

16
arch/arm/boot/dts/imx6dl-tqma6a.dtsi Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include "imx6dl.dtsi"
#include "imx6qdl-tqma6a.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
};

16
arch/arm/boot/dts/imx6dl-tqma6b.dtsi Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include "imx6dl.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
};

38
arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
View File

@ -8,6 +8,11 @@
#include <dt-bindings/pwm/pwm.h>
/ {
aliases: aliases {
ethernet1 = &eth1;
ethernet2 = &eth2;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
@ -135,13 +140,13 @@
};
};
port@2 {
eth2: port@2 {
reg = <2>;
label = "eth2";
phy-handle = <&phy_port2>;
};
port@3 {
eth1: port@3 {
reg = <3>;
label = "eth1";
phy-handle = <&phy_port3>;
@ -258,29 +263,35 @@
reg = <0x30>;
clock-mode = /bits/ 8 <1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
chan0 {
chan@0 {
chan-name = "R";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
reg = <0>;
};
chan1 {
chan@1 {
chan-name = "G";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
reg = <1>;
};
chan2 {
chan@2 {
chan-name = "B";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
reg = <2>;
};
chan3 {
chan@3 {
chan-name = "W";
led-cur = /bits/ 8 <0x0>;
max-cur = /bits/ 8 <0x0>;
reg = <3>;
};
};
@ -311,7 +322,20 @@
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
oled: oled@3d {
oled_1309: oled@3c {
compatible = "solomon,ssd1309fb-i2c";
reg = <0x3c>;
solomon,height = <64>;
solomon,width = <128>;
solomon,page-offset = <0>;
solomon,segment-no-remap;
solomon,prechargep2 = <15>;
reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
vbat-supply = <&sw2_reg>;
status = "disabled";
};
oled_1305: oled@3d {
compatible = "solomon,ssd1305fb-i2c";
reg = <0x3d>;
solomon,height = <64>;

6
arch/arm/boot/dts/imx6dl-yapp4-hydra.dts
View File

@ -29,7 +29,11 @@
status = "okay";
};
&oled {
&oled_1305 {
status = "okay";
};
&oled_1309 {
status = "okay";
};

54
arch/arm/boot/dts/imx6dl-yapp4-orion.dts Normal file
View File

@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2020 Y Soft Corporation, a.s.
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6dl-yapp4-common.dtsi"
/ {
model = "Y Soft IOTA Orion i.MX6DualLite board";
compatible = "ysoft,imx6dl-yapp4-orion", "fsl,imx6dl";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0xf0000000>;
};
};
&gpio_oled {
status = "okay";
};
&leds {
status = "okay";
};
&oled_1305 {
status = "okay";
};
&oled_1309 {
status = "okay";
};
&reg_usb_h1_vbus {
status = "okay";
};
&touchkeys {
status = "okay";
};
&uart2 {
status = "disabled";
};
&usbh1 {
status = "okay";
};
&usbphy2 {
status = "okay";
};

4
arch/arm/boot/dts/imx6dl-yapp4-ursa.dts
View File

@ -17,6 +17,10 @@
};
};
&aliases {
/delete-property/ ethernet1;
};
&backlight {
status = "okay";
};

8
arch/arm/boot/dts/imx6dl.dtsi
View File

@ -88,10 +88,6 @@
};
aips1: bus@2000000 {
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
pxp: pxp@20f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
@ -298,6 +294,10 @@
compatible = "fsl,imx6dl-hdmi";
};
&iomuxc {
compatible = "fsl,imx6dl-iomuxc";
};
&ipu1_csi1 {
ipu1_csi1_from_ipu1_csi1_mux: endpoint {
remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;

14
arch/arm/boot/dts/imx6q-b450v3.dts
View File

@ -84,19 +84,19 @@
};
&pca9539 {
P04 {
P04-hog {
gpio-hog;
gpios = <4 0>;
output-low;
line-name = "PCA9539-P04";
};
P07 {
gpio-hog;
gpios = <7 0>;
output-low;
line-name = "PCA9539-P07";
};
P07-hog {
gpio-hog;
gpios = <7 0>;
output-low;
line-name = "PCA9539-P07";
};
};
&pci_root {

12
arch/arm/boot/dts/imx6q-b650v3.dts
View File

@ -84,12 +84,12 @@
};
&pca9539 {
P07 {
gpio-hog;
gpios = <7 0>;
output-low;
line-name = "PCA9539-P07";
};
P07-hog {
gpio-hog;
gpios = <7 0>;
output-low;
line-name = "PCA9539-P07";
};
};
&usbphy1 {

4
arch/arm/boot/dts/imx6q-b850v3.dts
View File

@ -199,14 +199,14 @@
};
&pca9539 {
P10 {
P10-hog {
gpio-hog;
gpios = <8 0>;
output-low;
line-name = "PCA9539-P10";
};
P11 {
P11-hog {
gpio-hog;
gpios = <9 0>;
output-low;

2
arch/arm/boot/dts/imx6q-ba16.dtsi
View File

@ -134,7 +134,7 @@
};
&ecspi1 {
cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";

31
arch/arm/boot/dts/imx6q-bx50v3.dtsi
View File

@ -102,10 +102,15 @@
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
switch: switch@0 {
compatible = "marvell,mv88e6085"; /* 88e6240*/
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
switch_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
@ -117,22 +122,32 @@
switchphy0: switchphy@0 {
reg = <0>;
interrupt-parent = <&switch>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy1: switchphy@1 {
reg = <1>;
interrupt-parent = <&switch>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy2: switchphy@2 {
reg = <2>;
interrupt-parent = <&switch>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy3: switchphy@3 {
reg = <3>;
interrupt-parent = <&switch>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy4: switchphy@4 {
reg = <4>;
interrupt-parent = <&switch>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
@ -140,7 +155,7 @@
};
&ecspi5 {
cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
status = "okay";
@ -233,42 +248,42 @@
interrupt-parent = <&gpio2>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
P12 {
P12-hog {
gpio-hog;
gpios = <10 0>;
output-low;
line-name = "PCA9539-P12";
};
P13 {
P13-hog {
gpio-hog;
gpios = <11 0>;
output-low;
line-name = "PCA9539-P13";
};
P14 {
P14-hog {
gpio-hog;
gpios = <12 0>;
output-low;
line-name = "PCA9539-P14";
};
P15 {
P15-hog {
gpio-hog;
gpios = <13 0>;
output-low;
line-name = "PCA9539-P15";
};
P16 {
P16-hog {
gpio-hog;
gpios = <14 0>;
output-low;
line-name = "PCA9539-P16";
};
P17 {
P17-hog {
gpio-hog;
gpios = <15 0>;
output-low;

2
arch/arm/boot/dts/imx6q-cm-fx6.dts
View File

@ -255,7 +255,7 @@
};
&ecspi1 {
cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";

2
arch/arm/boot/dts/imx6q-dhcom-som.dtsi
View File

@ -59,7 +59,7 @@
};
&ecspi1 {
cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio4 11 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";

2
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
View File

@ -99,7 +99,7 @@
&ecspi5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
cs-gpios = <&gpio1 12 0>;
cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
flash: m25p80@0 {

2
arch/arm/boot/dts/imx6q-dms-ba16.dts
View File

@ -42,7 +42,7 @@
};
&ecspi5 {
cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
status = "okay";

2
arch/arm/boot/dts/imx6q-gw5400-a.dts
View File

@ -132,7 +132,7 @@
};
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";

7
arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi
View File

@ -14,10 +14,9 @@
/* Quad/Dual SoMs have 3 chip-select signals */
&ecspi4 {
fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>,
<&gpio3 29 GPIO_ACTIVE_HIGH>,
<&gpio3 25 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
<&gpio3 29 GPIO_ACTIVE_LOW>,
<&gpio3 25 GPIO_ACTIVE_LOW>;
};
&pinctrl_ecspi4 {

2
arch/arm/boot/dts/imx6q-logicpd.dts
View File

@ -9,7 +9,7 @@
/ {
model = "Logic PD i.MX6QD SOM-M3";
compatible = "fsl,imx6q";
compatible = "logicpd,imx6q-logicpd", "fsl,imx6q";
backlight: backlight-lvds {
compatible = "pwm-backlight";

6
arch/arm/boot/dts/imx6q-prti6q.dts
View File

@ -158,7 +158,7 @@
};
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@ -171,7 +171,7 @@
};
&ecspi2 {
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio4 25 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
status = "okay";
@ -195,7 +195,7 @@
};
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";

16
arch/arm/boot/dts/imx6q-tqma6a.dtsi Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include "imx6q.dtsi"
#include "imx6qdl-tqma6a.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
};

15
arch/arm/boot/dts/imx6q-tqma6b.dtsi Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*/
#include "imx6q.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
};

4
arch/arm/boot/dts/imx6q-var-dt6customboard.dts
View File

@ -144,8 +144,8 @@
};
&ecspi1 {
cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>,
<&gpio4 10 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>,
<&gpio4 10 GPIO_ACTIVE_LOW>;
status = "okay";
};

8
arch/arm/boot/dts/imx6q.dtsi
View File

@ -182,10 +182,6 @@
status = "disabled";
};
};
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6q-iomuxc";
};
};
sata: sata@2200000 {
@ -427,6 +423,10 @@
};
};
&iomuxc {
compatible = "fsl,imx6q-iomuxc";
};
&ipu1_csi1 {
ipu1_csi1_from_mipi_vc1: endpoint {
remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;

4
arch/arm/boot/dts/imx6qdl-apalis.dtsi
View File

@ -127,7 +127,7 @@
/* Apalis SPI1 */
&ecspi1 {
cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "disabled";
@ -135,7 +135,7 @@
/* Apalis SPI2 */
&ecspi2 {
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "disabled";

2
arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
View File

@ -91,7 +91,7 @@
};
&ecspi4 {
cs-gpios = <&gpio3 20 0>;
cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";

10
arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
View File

@ -110,23 +110,23 @@
};
&ecspi1 {
cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH
&gpio4 10 GPIO_ACTIVE_HIGH
&gpio4 11 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW
&gpio4 10 GPIO_ACTIVE_LOW
&gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
};
&ecspi2 {
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW &gpio2 27 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
};
&ecspi4 {
cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 29 GPIO_ACTIVE_LOW &gpio5 2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";

2
arch/arm/boot/dts/imx6qdl-colibri.dtsi
View File

@ -94,7 +94,7 @@
/* Colibri SSP */
&ecspi4 {
cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
status = "disabled";

2
arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
View File

@ -30,7 +30,7 @@
};
&ecspi3 {
cs-gpios = <&gpio4 24 0>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";

4
arch/arm/boot/dts/imx6qdl-emcon.dtsi
View File

@ -168,8 +168,8 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>,
<&gpio2 27 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>,
<&gpio2 27 GPIO_ACTIVE_LOW>;
};
&ecspi4 {

3
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@ -154,7 +155,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

5
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@ -182,7 +183,7 @@
};
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
@ -217,7 +218,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

3
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@ -210,7 +211,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

5
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
@ -212,7 +213,7 @@
};
&ecspi2 {
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
@ -247,7 +248,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;

3
arch/arm/boot/dts/imx6qdl-gw551x.dtsi
View File

@ -48,6 +48,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/tda1997x.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
@ -219,7 +220,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

3
arch/arm/boot/dts/imx6qdl-gw552x.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@ -144,7 +145,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

5
arch/arm/boot/dts/imx6qdl-gw553x.dtsi
View File

@ -47,6 +47,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@ -64,8 +65,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb {
label = "user_pb";
@ -182,7 +181,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

5
arch/arm/boot/dts/imx6qdl-gw560x.dtsi
View File

@ -47,6 +47,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@ -252,7 +253,7 @@
};
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
@ -294,7 +295,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

3
arch/arm/boot/dts/imx6qdl-gw5903.dtsi
View File

@ -47,6 +47,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
chosen {
@ -235,7 +236,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

3
arch/arm/boot/dts/imx6qdl-gw5904.dtsi
View File

@ -47,6 +47,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@ -257,7 +258,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

3
arch/arm/boot/dts/imx6qdl-gw5907.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@ -154,7 +155,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

5
arch/arm/boot/dts/imx6qdl-gw5910.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@ -134,7 +135,7 @@
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
@ -163,7 +164,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

5
arch/arm/boot/dts/imx6qdl-gw5912.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@ -129,7 +130,7 @@
};
&ecspi2 {
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
@ -158,7 +159,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;

3
arch/arm/boot/dts/imx6qdl-gw5913.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@ -139,7 +140,7 @@
compatible = "gw,gsc";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <4 GPIO_ACTIVE_LOW>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
#size-cells = <0>;

2
arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
View File

@ -203,7 +203,7 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>;
cs-gpios = <&gpio2 26 0>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
status = "okay";
};

8
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
View File

@ -245,16 +245,16 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>,
<&gpio2 27 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>,
<&gpio2 27 GPIO_ACTIVE_LOW>;
};
/* SPI0 */
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>,
<&gpio3 29 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
<&gpio3 29 GPIO_ACTIVE_LOW>;
status = "okay";
/* default boot source: workaround #1 for errata ERR006282 */

2
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
View File

@ -316,7 +316,7 @@
};
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";

2
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
View File

@ -247,7 +247,7 @@
};
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";

2
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
View File

@ -232,7 +232,7 @@
};
&ecspi1 {
cs-gpios = <&gpio3 19 0>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";

2
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
View File

@ -71,7 +71,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
cs-gpios = <&gpio4 24 0>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
som_flash: flash@0 {
compatible = "m25p80", "jedec,spi-nor";

2
arch/arm/boot/dts/imx6qdl-pico.dtsi
View File

@ -167,7 +167,7 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
View File

@ -267,7 +267,7 @@
};
&ecspi1 {
cs-gpios = <&gpio3 19 0>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
status = "disabled"; /* pin conflict with WEIM NOR */

2
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
View File

@ -308,7 +308,7 @@
};
&ecspi1 {
cs-gpios = <&gpio3 19 0>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";

8
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View File

@ -105,9 +105,13 @@
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
"IN3R", "AMIC",
"DMIC", "MICBIAS",
"DMICDAT", "DMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>;
mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
};
backlight_lvds: backlight-lvds {
@ -185,7 +189,7 @@
};
&ecspi1 {
cs-gpios = <&gpio4 9 0>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";

201
arch/arm/boot/dts/imx6qdl-tqma6.dtsi Normal file
View File

@ -0,0 +1,201 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "supply-3p3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
status = "okay";
m25p80: flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
m25p,fast-read;
};
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
/* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099
/* eCSPI1 SS1 */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
};
&pmic {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio6>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
regulators {
reg_vddcore: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_vddsoc: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_gen_3v3: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_ddr_1v5a: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_ddr_1v5b: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5v_600mA: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-always-on;
};
reg_snvs_3v: vsnvs {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
reg_vrefddr: vrefddr {
regulator-boot-on;
regulator-always-on;
};
reg_vgen1_1v5: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
/* not used */
};
reg_vgen2_1v2_eth: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
reg_vgen3_2v8: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen4_1v8: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen5_1v8_eth: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen6_3v3: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
vmmc-supply = <&reg_3p3v>;
non-removable;
disable-wp;
no-sd;
no-sdio;
bus-width = <8>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
mmccard: mmccard@0 {
reg = <0>;
compatible = "mmc-card";
broken-hpi;
};
};

28
arch/arm/boot/dts/imx6qdl-tqma6a.dtsi Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <100000>;
status = "okay";
pmic: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
};
sensor@48 {
compatible = "national,lm75";
reg = <0x48>;
};
eeprom@50 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
};

28
arch/arm/boot/dts/imx6qdl-tqma6b.dtsi Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <100000>;
status = "okay";
pmic: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
};
sensor@48 {
compatible = "national,lm75";
reg = <0x48>;
};
eeprom@50 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
};

4
arch/arm/boot/dts/imx6qdl-ts4900.dtsi
View File

@ -95,7 +95,7 @@
};
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@ -108,7 +108,7 @@
};
&ecspi2 {
cs-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";

8
arch/arm/boot/dts/imx6qdl-ts7970.dtsi
View File

@ -165,7 +165,7 @@
};
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@ -179,9 +179,9 @@
&ecspi2 {
cs-gpios = <
&gpio5 31 GPIO_ACTIVE_HIGH
&gpio7 12 GPIO_ACTIVE_HIGH
&gpio5 18 GPIO_ACTIVE_HIGH
&gpio5 31 GPIO_ACTIVE_LOW
&gpio7 12 GPIO_ACTIVE_LOW
&gpio5 18 GPIO_ACTIVE_LOW
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;

2
arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
View File

@ -316,7 +316,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {

5
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -159,7 +159,7 @@
clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
};
gpmi: gpmi-nand@112000 {
gpmi: nand-controller@112000 {
compatible = "fsl,imx6q-gpmi-nand";
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
reg-names = "gpmi-nand", "bch";
@ -1043,8 +1043,9 @@
<0 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp";
clock-names = "ipg", "ahb", "ptp", "enet_out";
fsl,stop-mode = <&gpr 0x34 27>;
status = "disabled";
};

3
arch/arm/boot/dts/imx6qp-sabreauto.dts
View File

@ -47,7 +47,8 @@
};
&pcie {
status = "disabled";
reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
status = "okay";
};
&sata {

16
arch/arm/boot/dts/imx6qp-tqma6b.dtsi Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*/
#include "imx6q.dtsi"
#include "imx6qp.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
};

11
arch/arm/boot/dts/imx6sl-evk.dts
View File

@ -94,6 +94,8 @@
sound {
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hp>;
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
@ -106,6 +108,7 @@
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
};
panel {
@ -129,7 +132,7 @@
};
&ecspi1 {
cs-gpios = <&gpio4 11 0>;
cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@ -343,6 +346,12 @@
>;
};
pinctrl_hp: hpgrp {
fsl,pins = <
MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1

588
arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts Normal file
View File

@ -0,0 +1,588 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device tree for the Tolino Shine 2 HD ebook reader
*
* Name on mainboard is: 37NB-E60QF0+4A2 or 37NB-E60QF0+4A3
* Serials start with: E60QF2
*
* Copyright 2020 Andreas Kemnade
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx6sl.dtsi"
/ {
model = "Tolino Shine 2 HD";
compatible = "kobo,tolino-shine2hd", "fsl,imx6sl";
chosen {
stdout-path = &uart1;
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
cover {
label = "Cover";
gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
linux,code = <SW_LID>;
linux,input-type = <EV_SW>;
wakeup-source;
};
fl {
label = "Frontlight";
gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BRIGHTNESS_CYCLE>;
};
home {
label = "Home";
gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
power {
label = "Power";
gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds: leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
on {
label = "tolinoshine2hd:white:on";
gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
reg_wifi: regulator-wifi {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_power>;
regulator-name = "SD3_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_reset>;
post-power-on-delay-ms = <20>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
};
};
&i2c1 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_sleep>;
status = "okay";
/* TODO: embedded controller at 0x43 (driver missing) */
};
&i2c2 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_sleep>;
clock-frequency = <100000>;
status = "okay";
zforce: touchscreen@50 {
compatible = "neonode,zforce";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_zforce>;
reg = <0x50>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&ldo1_reg>;
reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
x-size = <1072>;
y-size = <1448>;
};
/* TODO: TPS65185 PMIC for E Ink at 0x68 */
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <400000>;
status = "okay";
ricoh619: pmic@32 {
compatible = "ricoh,rc5t619";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ricoh_gpio>;
reg = <0x32>;
interrupt-parent = <&gpio5>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
system-power-controller;
regulators {
dcdc1_reg: DCDC1 {
regulator-name = "DCDC1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <900000>;
regulator-suspend-min-microvolt = <900000>;
};
};
/* Core3_3V3 */
dcdc2_reg: DCDC2 {
regulator-name = "DCDC2";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <3100000>;
regulator-suspend-min-microvolt = <3100000>;
};
};
dcdc3_reg: DCDC3 {
regulator-name = "DCDC3";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1140000>;
regulator-suspend-min-microvolt = <1140000>;
};
};
/* Core4_1V2 */
dcdc4_reg: DCDC4 {
regulator-name = "DCDC4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1140000>;
regulator-suspend-min-microvolt = <1140000>;
};
};
/* Core4_1V8 */
dcdc5_reg: DCDC5 {
regulator-name = "DCDC5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <1700000>;
regulator-suspend-min-microvolt = <1700000>;
};
};
/* IR_3V3 */
ldo1_reg: LDO1 {
regulator-name = "LDO1";
regulator-boot-on;
};
/* Core1_3V3 */
ldo2_reg: LDO2 {
regulator-name = "LDO2";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-max-microvolt = <3000000>;
regulator-suspend-min-microvolt = <3000000>;
};
};
/* Core5_1V2 */
ldo3_reg: LDO3 {
regulator-name = "LDO3";
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: LDO4 {
regulator-name = "LDO4";
regulator-boot-on;
};
/* SPD_3V3 */
ldo5_reg: LDO5 {
regulator-name = "LDO5";
regulator-always-on;
regulator-boot-on;
};
/* DDR_0V6 */
ldo6_reg: LDO6 {
regulator-name = "LDO6";
regulator-always-on;
regulator-boot-on;
};
/* VDD_PWM */
ldo7_reg: LDO7 {
regulator-name = "LDO7";
regulator-always-on;
regulator-boot-on;
};
/* ldo_1v8 */
ldo8_reg: LDO8 {
regulator-name = "LDO8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo9_reg: LDO9 {
regulator-name = "LDO9";
regulator-boot-on;
};
ldo10_reg: LDO10 {
regulator-name = "LDO10";
regulator-boot-on;
};
ldortc1_reg: LDORTC1 {
regulator-name = "LDORTC1";
regulator-always-on;
regulator-boot-on;
};
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059
MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059
MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x17059
MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x17059
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79
MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79
MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79
MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79
MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79
MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79
MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79
MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79
MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79
MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79
MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79
MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79
MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79
MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79
MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79
MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79
MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79
MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79
MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79
MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79
MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79
MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79
MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79
MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79
MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79
MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79
MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79
MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79
MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79
MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x79
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
>;
};
pinctrl_i2c1_sleep: i2c1grp-sleep {
fsl,pins = <
MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
>;
};
pinctrl_i2c2_sleep: i2c2grp-sleep {
fsl,pins = <
MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059
>;
};
pinctrl_ricoh_gpio: ricoh_gpiogrp {
fsl,pins = <
MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */
MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
>;
};
pinctrl_usdhc2_sleep: usdhc2grp-sleep {
fsl,pins = <
MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9
MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9
MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9
MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9
MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9
MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059
MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
>;
};
pinctrl_usdhc3_sleep: usdhc3grp-sleep {
fsl,pins = <
MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1
MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1
MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1
MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1
>;
};
pinctrl_wifi_power: wifi-powergrp {
fsl,pins = <
MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
>;
};
pinctrl_wifi_reset: wifi-resetgrp {
fsl,pins = <
MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */
>;
};
pinctrl_zforce: zforcegrp {
fsl,pins = <
MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */
MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x10059 /* TP_RST */
>;
};
};
&reg_vdd1p1 {
vin-supply = <&dcdc2_reg>;
};
&reg_vdd2p5 {
vin-supply = <&dcdc2_reg>;
};
&reg_arm {
vin-supply = <&dcdc3_reg>;
};
&reg_soc {
vin-supply = <&dcdc1_reg>;
};
&reg_pu {
vin-supply = <&dcdc1_reg>;
};
&snvs_rtc {
/*
* We are using the RTC in the PMIC, but this one is not disabled
* in imx6sl.dtsi.
*/
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>;
non-removable;
status = "okay";
/* internal uSD card */
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
pinctrl-3 = <&pinctrl_usdhc3_sleep>;
vmmc-supply = <&reg_wifi>;
mmc-pwrseq = <&wifi_pwrseq>;
cap-power-off-card;
non-removable;
status = "okay";
/*
* 37NB-E60QF0+4A2: CyberTan WC121 (BCM43362) SDIO WiFi
* 37NB-E60QF0+4A3: RTL8189F SDIO WiFi
*/
};
&usbotg1 {
pinctrl-names = "default";
disable-over-current;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};

2
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -939,8 +939,10 @@
};
rngb: rngb@21b4000 {
compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
reg = <0x021b4000 0x4000>;
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
};
weim: weim@21b8000 {

73
arch/arm/boot/dts/imx6sll-evk.dts
View File

@ -132,6 +132,31 @@
};
};
};
sound {
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hp>;
model = "wm8962-audio";
audio-cpu = <&ssi2>;
audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux3>;
status = "okay";
};
&cpu0 {
@ -247,6 +272,27 @@
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
DCVDD-supply = <&vgen3_reg>;
DBVDD-supply = <&reg_aud3v>;
AVDD-supply = <&vgen3_reg>;
CPVDD-supply = <&vgen3_reg>;
MICVDD-supply = <&reg_aud3v>;
PLLVDD-supply = <&vgen3_reg>;
SPKVDD1-supply = <&reg_aud4v>;
SPKVDD2-supply = <&reg_aud4v>;
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
@ -274,6 +320,10 @@
status = "okay";
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@ -330,6 +380,22 @@
};
&iomuxc {
pinctrl_audmux3: audmux3grp {
fsl,pins = <
MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
>;
};
pinctrl_hp: hpgrp {
fsl,pins = <
MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
>;
};
pinctrl_reg_sd3_vmmc: sd3vmmcgrp {
fsl,pins = <
MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059
@ -449,6 +515,13 @@
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1
MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79

7
arch/arm/boot/dts/imx6sll.dtsi
View File

@ -786,6 +786,13 @@
clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
};
rngb: rng@21b4000 {
compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb";
reg = <0x021b4000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_DUMMY>;
};
ocotp: efuse@21bc000 {
#address-cells = <1>;
#size-cells = <1>;

9
arch/arm/boot/dts/imx6sx-sdb.dtsi
View File

@ -153,6 +153,8 @@
sound {
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hp>;
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
@ -165,6 +167,7 @@
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <6>;
hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
panel {
@ -468,6 +471,12 @@
>;
};
pinctrl_hp: hpgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1

2
arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
View File

@ -93,7 +93,7 @@
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -213,7 +213,7 @@
clocks = <&clks IMX6SX_CLK_APBH_DMA>;
};
gpmi: gpmi-nand@1806000{
gpmi: nand-controller@1806000{
compatible = "fsl,imx6sx-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi
View File

@ -84,7 +84,7 @@
};
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";

2
arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi
View File

@ -14,7 +14,7 @@
};
&ecspi2 {
cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";

2
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
View File

@ -106,7 +106,7 @@
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
status = "disabled";
};

2
arch/arm/boot/dts/imx6ul.dtsi
View File

@ -174,7 +174,7 @@
clocks = <&clks IMX6UL_CLK_APBHDMA>;
};
gpmi: gpmi-nand@1806000 {
gpmi: nand-controller@1806000 {
compatible = "fsl,imx6q-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm/boot/dts/imx6ull-colibri.dtsi
View File

@ -68,7 +68,7 @@
/* Colibri SPI */
&ecspi1 {
cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
};

Some files were not shown because too many files have changed in this diff Show More