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i2c: qup: Cleared the error bits in ISR

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1. Current QCOM I2C driver hangs when sending data to address 0x03-0x07
in some scenarios. The QUP controller generates invalid write in this
case, since these addresses are reserved for different bus formats.

2. Also, the error handling is done by I2C QUP ISR in the case of DMA
mode. The state need to be RESET in case of any error for clearing the
available data in FIFO, which otherwise leaves the BAM DMA controller
in hang state.

This patch fixes the above two issues by clearing the error bits from
I2C and QUP status in ISR in case of I2C error, QUP error and resets
the QUP state to clear the FIFO data.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Abhishek Sahu
2016-05-09 18:14:30 +05:30
committed by Wolfram Sang
parent 94a0b0b92e
commit 2b84a4dd4b
1 changed files with 8 additions and 6 deletions
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14
drivers/i2c/busses/i2c-qup.c
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@ -213,14 +213,16 @@ static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
bus_err &= I2C_STATUS_ERROR_MASK; bus_err &= I2C_STATUS_ERROR_MASK;
qup_err &= QUP_STATUS_ERROR_FLAGS; qup_err &= QUP_STATUS_ERROR_FLAGS;
if (qup_err) { /* Clear the error bits in QUP_ERROR_FLAGS */
/* Clear Error interrupt */ if (qup_err)
writel(qup_err, qup->base + QUP_ERROR_FLAGS); writel(qup_err, qup->base + QUP_ERROR_FLAGS);
goto done;
}
if (bus_err) { /* Clear the error bits in QUP_I2C_STATUS */
/* Clear Error interrupt */ if (bus_err)
writel(bus_err, qup->base + QUP_I2C_STATUS);
/* Reset the QUP State in case of error */
if (qup_err || bus_err) {
writel(QUP_RESET_STATE, qup->base + QUP_STATE); writel(QUP_RESET_STATE, qup->base + QUP_STATE);
goto done; goto done;
} }