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dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

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Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12869/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Antony Pavlov 2016-03-17 06:34:08 +03:00 committed by Ralf Baechle
parent 3b143cca6e
commit 2b885ea66f
2 changed files with 4 additions and 4 deletions
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6
Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
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@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
Required Properties: Required Properties:
- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following - compatible: has to be "qca,<soctype>-pll" and one of the following
fallbacks: fallbacks:
- "qca,ar7100-pll" - "qca,ar7100-pll"
- "qca,ar7240-pll" - "qca,ar7240-pll"
@ -21,8 +21,8 @@ Optional properties:
Example: Example:
memory-controller@18050000 { pll-controller@18050000 {
compatible = "qca,ar9132-ppl", "qca,ar9130-pll"; compatible = "qca,ar9132-pll", "qca,ar9130-pll";
reg = <0x18050000 0x20>; reg = <0x18050000 0x20>;
clock-names = "ref"; clock-names = "ref";

2
arch/mips/boot/dts/qca/ar9132.dtsi
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@ -83,7 +83,7 @@
}; };
pll: pll-controller@18050000 { pll: pll-controller@18050000 {
compatible = "qca,ar9132-ppl", compatible = "qca,ar9132-pll",
"qca,ar9130-pll"; "qca,ar9130-pll";
reg = <0x18050000 0x20>; reg = <0x18050000 0x20>;