arm64: dts: rockchip: fix pd_tcpc0 and pd_tcpc1 node position on rk3399
The pd_tcpc0 and pd_tcpc1 nodes are currently a sub node of pd_vio. In the rk3399 TRM figure of the 'Power Domain Partition' and in the table of 'Power Domain and Voltage Domain Summary' these power domains are positioned directly under VD_LOGIC, so fix that in 'rk3399.dtsi'. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Caesar Wang <wxt@rock-chips.com> Link: https://lore.kernel.org/r/20200428203003.3318-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -1056,6 +1056,16 @@
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clocks = <&cru HCLK_SDIO>;
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pm_qos = <&qos_sdioaudio>;
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};
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pd_tcpc0@RK3399_PD_TCPD0 {
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reg = <RK3399_PD_TCPD0>;
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clocks = <&cru SCLK_UPHY0_TCPDCORE>,
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<&cru SCLK_UPHY0_TCPDPHY_REF>;
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};
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pd_tcpc1@RK3399_PD_TCPD1 {
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reg = <RK3399_PD_TCPD1>;
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clocks = <&cru SCLK_UPHY1_TCPDCORE>,
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<&cru SCLK_UPHY1_TCPDPHY_REF>;
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};
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pd_usb3@RK3399_PD_USB3 {
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reg = <RK3399_PD_USB3>;
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clocks = <&cru ACLK_USB3>;
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@ -1088,16 +1098,6 @@
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pm_qos = <&qos_isp1_m0>,
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<&qos_isp1_m1>;
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};
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pd_tcpc0@RK3399_PD_TCPD0 {
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reg = <RK3399_PD_TCPD0>;
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clocks = <&cru SCLK_UPHY0_TCPDCORE>,
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<&cru SCLK_UPHY0_TCPDPHY_REF>;
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};
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pd_tcpc1@RK3399_PD_TCPD1 {
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reg = <RK3399_PD_TCPD1>;
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clocks = <&cru SCLK_UPHY1_TCPDCORE>,
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<&cru SCLK_UPHY1_TCPDPHY_REF>;
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};
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pd_vo@RK3399_PD_VO {
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reg = <RK3399_PD_VO>;
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#address-cells = <1>;
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