clk: rockchip: Fix PLL bandwidth
In the TRM we see that BWADJ is "a 12-bit bus that selects the values 1-4096 for the bandwidth divider (NB)": NB = BWADJ[11:0] + 1 The recommended setting of NB: NB = NF / 2. So: NB = NF / 2 BWADJ[11:0] + 1 = NF / 2 BWADJ[11:0] = NF / 2 - 1 Right now, we have: { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ .bwadj = (_nf >> 1), \ } That means we set bwadj to NF / 2, not NF / 2 - 1 All of this is a bit confusing because we specify "NR" (the 1-based value), "NF" (the 1-based value), "NO" (the 1-based value), but "BWADJ" (the 0-based value) instead of "NB" (the 1-based value). Let's change to working with "NB" and fix the off by one error. This may affect PLL jitter in a small way (hopefully for the better). Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -120,8 +120,8 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
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#define RK3066_PLLCON0_NR_SHIFT 8
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#define RK3066_PLLCON1_NF_MASK 0x1fff
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#define RK3066_PLLCON1_NF_SHIFT 0
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#define RK3066_PLLCON2_BWADJ_MASK 0xfff
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#define RK3066_PLLCON2_BWADJ_SHIFT 0
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#define RK3066_PLLCON2_NB_MASK 0xfff
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#define RK3066_PLLCON2_NB_SHIFT 0
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#define RK3066_PLLCON3_RESET (1 << 5)
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#define RK3066_PLLCON3_PWRDOWN (1 << 1)
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#define RK3066_PLLCON3_BYPASS (1 << 0)
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@ -207,8 +207,8 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
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writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
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RK3066_PLLCON1_NF_SHIFT),
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pll->reg_base + RK3066_PLLCON(1));
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writel_relaxed(HIWORD_UPDATE(rate->bwadj, RK3066_PLLCON2_BWADJ_MASK,
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RK3066_PLLCON2_BWADJ_SHIFT),
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writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
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RK3066_PLLCON2_NB_SHIFT),
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pll->reg_base + RK3066_PLLCON(2));
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/* leave reset and wait the reset_delay */
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@ -261,7 +261,7 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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const struct rockchip_pll_rate_table *rate;
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unsigned int nf, nr, no, bwadj;
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unsigned int nf, nr, no, nb;
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unsigned long drate;
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u32 pllcon;
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@ -283,13 +283,13 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw)
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nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK) + 1;
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pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
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bwadj = (pllcon >> RK3066_PLLCON2_BWADJ_SHIFT) & RK3066_PLLCON2_BWADJ_MASK;
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nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) & RK3066_PLLCON2_NB_MASK) + 1;
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pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), bwadj(%d:%d)\n",
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pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
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__func__, __clk_get_name(hw->clk), drate, rate->nr, nr,
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rate->no, no, rate->nf, nf, rate->bwadj, bwadj);
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rate->no, no, rate->nf, nf, rate->nb, nb);
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if (rate->nr != nr || rate->no != no || rate->nf != nf
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|| rate->bwadj != bwadj) {
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|| rate->nb != nb) {
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struct clk *parent = __clk_get_parent(hw->clk);
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unsigned long prate;
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@ -817,7 +817,7 @@ static void __init rk3188_clk_init(struct device_node *np)
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rate = pll->rate_table;
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while (rate->rate > 0) {
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rate->bwadj = 0;
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rate->nb = 1;
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rate++;
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}
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}
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@ -84,7 +84,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
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RK3066_PLL_RATE( 742500000, 8, 495, 2),
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RK3066_PLL_RATE( 696000000, 1, 58, 2),
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RK3066_PLL_RATE( 600000000, 1, 50, 2),
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RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
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RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
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RK3066_PLL_RATE( 552000000, 1, 46, 2),
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RK3066_PLL_RATE( 504000000, 1, 84, 4),
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RK3066_PLL_RATE( 500000000, 3, 125, 2),
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@ -83,16 +83,16 @@ enum rockchip_pll_type {
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.nr = _nr, \
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.nf = _nf, \
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.no = _no, \
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.bwadj = ((_nf) >> 1), \
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.nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
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}
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#define RK3066_PLL_RATE_BWADJ(_rate, _nr, _nf, _no, _bw) \
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#define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
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{ \
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.rate = _rate##U, \
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.nr = _nr, \
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.nf = _nf, \
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.no = _no, \
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.bwadj = _bw, \
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.nb = _nb, \
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}
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struct rockchip_pll_rate_table {
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@ -100,7 +100,7 @@ struct rockchip_pll_rate_table {
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unsigned int nr;
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unsigned int nf;
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unsigned int no;
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unsigned int bwadj;
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unsigned int nb;
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};
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/**
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