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Renesas ARM DT updates for v5.9 (take two)

Browse Source 
- SPI Multi I/O Bus Controller (RPC-IF) support for R-Car V3H and V3M,
     including QSPI support for the Condor, Eagle, V3HSK, and V3MSK
     boards,
   - Initial support for the RZ/G2H SoC on the HopeRun HiHope RZ/G2H
     board,
   - Initial support for the Beacon EmbeddedWorks RZ/G2M board,
   - Minor fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.9 (take two)

  - SPI Multi I/O Bus Controller (RPC-IF) support for R-Car V3H and V3M,
    including QSPI support for the Condor, Eagle, V3HSK, and V3MSK
    boards,
  - Initial support for the RZ/G2H SoC on the HopeRun HiHope RZ/G2H
    board,
  - Initial support for the Beacon EmbeddedWorks RZ/G2M board,
  - Minor fixes and improvements.

* tag 'renesas-arm-dt-for-v5.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits)
  ARM: dts: sh73a0: Add missing clocks to sound node
  arm64: dts: renesas: r8a774e1: Add CAN[FD] support
  arm64: dts: renesas: r8a774e1: Add RWDT node
  arm64: dts: renesas: r8a774e1: Add MSIOF nodes
  arm64: dts: renesas: r8a774e1: Add I2C and IIC-DVFS support
  arm64: dts: renesas: r8a774e1: Add SDHI nodes
  arm64: dts: renesas: r8a774e1: Add SCIF and HSCIF nodes
  arm64: dts: renesas: r8a774e1: Add TMU device nodes
  arm64: dts: renesas: r8a774e1: Add CMT device nodes
  arm64: dts: renesas: r8a774e1: Add RZ/G2H thermal support
  arm64: dts: renesas: r8a774e1: Add operating points
  arm64: dts: renesas: Introduce r8a774a1-beacon-rzg2m-kit
  arm64: dts: renesas: r8a774e1: Add Ethernet AVB node
  arm64: dts: renesas: r8a774e1: Add GPIO device nodes
  arm64: dts: renesas: r8a774e1: Add SYS-DMAC device nodes
  arm64: dts: renesas: r8a774e1: Add IPMMU device nodes
  ARM: dts: gose: Fix ports node name for adv7612
  ARM: dts: renesas: Fix SD Card/eMMC interface device node names
  arm64: dts: renesas: Fix SD Card/eMMC interface device node names
  arm64: dts: renesas: add full-pwr-cycle-in-suspend into eMMC nodes
  ...

Link: https://lore.kernel.org/r/20200717112427.26032-2-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-07-17 15:36:23 +02:00
commit 2c2a5564d1
54 changed files with 3342 additions and 119 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/r7s72100.dtsi
View File

@ -323,7 +323,7 @@
status = "disabled";
};
sdhi0: sd@e804e000 {
sdhi0: mmc@e804e000 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e000 0x100>;
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
@ -339,7 +339,7 @@
status = "disabled";
};
sdhi1: sd@e804e800 {
sdhi1: mmc@e804e800 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e800 0x100>;
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,

4
arch/arm/boot/dts/r7s9210.dtsi
View File

@ -416,7 +416,7 @@
status = "disabled";
};
sdhi0: sd@e8228000 {
sdhi0: mmc@e8228000 {
compatible = "renesas,sdhi-r7s9210";
reg = <0xe8228000 0x8c0>;
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
@ -428,7 +428,7 @@
status = "disabled";
};
sdhi1: sd@e822a000 {
sdhi1: mmc@e822a000 {
compatible = "renesas,sdhi-r7s9210";
reg = <0xe822a000 0x8c0>;
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;

6
arch/arm/boot/dts/r8a73a4.dtsi
View File

@ -409,7 +409,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee100000 0 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
@ -419,7 +419,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee120000 0 0x100>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
@ -429,7 +429,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

6
arch/arm/boot/dts/r8a7740.dtsi
View File

@ -349,7 +349,7 @@
status = "disabled";
};
sdhi0: sd@e6850000 {
sdhi0: mmc@e6850000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6850000 0x100>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
@ -362,7 +362,7 @@
status = "disabled";
};
sdhi1: sd@e6860000 {
sdhi1: mmc@e6860000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6860000 0x100>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
@ -375,7 +375,7 @@
status = "disabled";
};
sdhi2: sd@e6870000 {
sdhi2: mmc@e6870000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6870000 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

8
arch/arm/boot/dts/r8a7742.dtsi
View File

@ -1286,7 +1286,7 @@
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1301,7 +1301,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee120000 0 0x328>;
@ -1316,7 +1316,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1331,7 +1331,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;

6
arch/arm/boot/dts/r8a7743.dtsi
View File

@ -1520,7 +1520,7 @@
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1535,7 +1535,7 @@
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1550,7 +1550,7 @@
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;

6
arch/arm/boot/dts/r8a7744.dtsi
View File

@ -1520,7 +1520,7 @@
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7744",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1535,7 +1535,7 @@
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7744",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1550,7 +1550,7 @@
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7744",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;

6
arch/arm/boot/dts/r8a7745.dtsi
View File

@ -1396,7 +1396,7 @@
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1411,7 +1411,7 @@
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1426,7 +1426,7 @@
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;

6
arch/arm/boot/dts/r8a77470.dtsi
View File

@ -882,7 +882,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a77470",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -897,7 +897,7 @@
status = "disabled";
};
sdhi1: sd@ee300000 {
sdhi1: mmc@ee300000 {
compatible = "renesas,sdhi-mmc-r8a77470";
reg = <0 0xee300000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
@ -908,7 +908,7 @@
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a77470",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x328>;

6
arch/arm/boot/dts/r8a7778.dtsi
View File

@ -401,7 +401,7 @@
status = "disabled";
};
sdhi0: sd@ffe4c000 {
sdhi0: mmc@ffe4c000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4c000 0x100>;
@ -411,7 +411,7 @@
status = "disabled";
};
sdhi1: sd@ffe4d000 {
sdhi1: mmc@ffe4d000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4d000 0x100>;
@ -421,7 +421,7 @@
status = "disabled";
};
sdhi2: sd@ffe4f000 {
sdhi2: mmc@ffe4f000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4f000 0x100>;

8
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -385,7 +385,7 @@
status = "disabled";
};
sdhi0: sd@ffe4c000 {
sdhi0: mmc@ffe4c000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4c000 0x100>;
@ -395,7 +395,7 @@
status = "disabled";
};
sdhi1: sd@ffe4d000 {
sdhi1: mmc@ffe4d000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4d000 0x100>;
@ -405,7 +405,7 @@
status = "disabled";
};
sdhi2: sd@ffe4e000 {
sdhi2: mmc@ffe4e000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4e000 0x100>;
@ -415,7 +415,7 @@
status = "disabled";
};
sdhi3: sd@ffe4f000 {
sdhi3: mmc@ffe4f000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4f000 0x100>;

1
arch/arm/boot/dts/r8a7790-lager.dts
View File

@ -343,7 +343,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin1>;
port {
adv7180: endpoint {

8
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -1467,7 +1467,7 @@
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1482,7 +1482,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee120000 0 0x328>;
@ -1497,7 +1497,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1512,7 +1512,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;

1
arch/arm/boot/dts/r8a7791-koelsch.dts
View File

@ -366,7 +366,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin1>;
port {
adv7180: endpoint {

1
arch/arm/boot/dts/r8a7791-porter.dts
View File

@ -162,7 +162,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {

6
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -1563,7 +1563,7 @@
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1578,7 +1578,7 @@
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1593,7 +1593,7 @@
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;

2
arch/arm/boot/dts/r8a7792.dtsi
View File

@ -780,7 +780,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7792",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;

5
arch/arm/boot/dts/r8a7793-gose.dts
View File

@ -334,9 +334,8 @@
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
remote = <&vin1>;
port {
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -394,7 +393,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
default-input = <0>;
port {
ports {
#address-cells = <1>;
#size-cells = <0>;

6
arch/arm/boot/dts/r8a7793.dtsi
View File

@ -1227,7 +1227,7 @@
dma-channels = <13>;
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1242,7 +1242,7 @@
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1257,7 +1257,7 @@
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;

1
arch/arm/boot/dts/r8a7794-alt.dts
View File

@ -167,7 +167,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {

1
arch/arm/boot/dts/r8a7794-silk.dts
View File

@ -236,7 +236,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {

6
arch/arm/boot/dts/r8a7794.dtsi
View File

@ -1232,7 +1232,7 @@
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1247,7 +1247,7 @@
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1262,7 +1262,7 @@
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;

7
arch/arm/boot/dts/sh73a0.dtsi
View File

@ -321,7 +321,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee100000 0x100>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
@ -334,7 +334,7 @@
};
/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee120000 0x100>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
@ -346,7 +346,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee140000 0x100>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@ -584,6 +584,7 @@
compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
reg = <0xec230000 0x400>;
interrupts = <GIC_SPI 146 0x4>;
clocks = <&mstp3_clks SH73A0_CLK_FSI>;
power-domains = <&pd_a4mp>;
status = "disabled";
};

73
arch/arm64/boot/dts/renesas/Makefile
View File

@ -1,30 +1,55 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb \
r8a774a1-hihope-rzg2m-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb \
r8a774a1-hihope-rzg2m-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb \
r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb \
r8a774b1-hihope-rzg2n-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb \
r8a774b1-hihope-rzg2n-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb \
r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \
r8a774c0-ek874-idk-2121wr.dtb \
r8a774c0-ek874-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-beacon-rzg2m-kit.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-idk-2121wr.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb r8a77950-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb r8a77951-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb r8a77951-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x.dtb r8a77960-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb.dtb r8a77960-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb r8a77965-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-v3msk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Compass Electronics Group, LLC
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
power-supply = <&reg_lcd>;
enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_LOW>;
pwms = <&pwm2 0 50000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
backlight_rgb: backlight-rgb {
compatible = "pwm-backlight";
power-supply = <&reg_lcd>;
enable-gpios = <&gpio_exp1 7 GPIO_ACTIVE_LOW>;
pwms = <&pwm0 0 50000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
hdmi0-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con: endpoint {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
};
};
keys {
compatible = "gpio-keys";
key-1 {
gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "Switch-1";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "Switch-2";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "Switch-3";
wakeup-source;
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "Switch-4";
wakeup-source;
debounce-interval = <20>;
};
key-5 {
gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
linux,code = <KEY_5>;
label = "Switch-4";
wakeup-source;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led0 {
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
label = "LED0";
linux,default-trigger = "heartbeat";
};
led1 {
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
label = "LED1";
};
led2 {
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
label = "LED2";
};
led3 {
gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
label = "LED3";
};
};
lvds {
compatible = "panel-lvds";
power-supply = <&reg_lcd_reset>;
width-mm = <223>;
height-mm = <125>;
backlight = <&backlight_lvds>;
data-mapping = "vesa-24";
panel-timing {
/* 800x480@60Hz */
clock-frequency = <30000000>;
hactive = <800>;
vactive = <480>;
hsync-len = <48>;
hfront-porch = <40>;
hback-porch = <40>;
vfront-porch = <13>;
vback-porch = <29>;
vsync-len = <3>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <0>;
};
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
rgb {
/* Different LCD with compatible timings */
compatible = "rocktech,rk070er9427";
backlight = <&backlight_rgb>;
enable-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_lcd>;
port {
rgb_panel: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
};
reg_audio: regulator_audio {
compatible = "regulator-fixed";
regulator-name = "audio-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio_exp2 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_lcd: regulator-lcd {
compatible = "regulator-fixed";
regulator-name = "lcd_panel_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_exp1 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_lcd_reset: regulator-lcd-reset {
compatible = "regulator-fixed";
regulator-name = "nLCD_RESET";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_lcd>;
};
reg_cam0: regulator_camera {
compatible = "regulator-fixed";
regulator-name = "reg_cam0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio_exp2 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_cam1: regulator_camera {
compatible = "regulator-fixed";
regulator-name = "reg_cam1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio_exp2 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100000>;
};
sound_card {
compatible = "audio-graph-card";
label = "rcar-sound";
dais = <&rsnd_port0>, <&rsnd_port1>;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
regulator-always-on;
};
/* External DU dot clocks */
x302_clk: x302-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33000000>;
};
x304_clk: x304-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
&audio_clk_a {
clock-frequency = <24576000>;
assigned-clocks = <&versaclock6_bb 4>;
assigned-clock-rates = <24576000>;
};
&audio_clk_b {
clock-frequency = <22579200>;
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
renesas,can-clock-select = <0x0>;
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
renesas,can-clock-select = <0x0>;
status = "okay";
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&du_out_rgb {
remote-endpoint = <&rgb_panel>;
};
&ehci0 {
dr_mode = "otg";
status = "okay";
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
};
&ehci1 {
status = "okay";
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
};
&hdmi0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dw_hdmi0_in: endpoint {
remote-endpoint = <&du_out_hdmi0>;
};
};
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c2 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
gpio_exp2: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_exp3: gpio@22 {
compatible = "onnn,pca9654";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_exp4: gpio@23 {
compatible = "onnn,pca9654";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
versaclock6_bb: clock-controller@6a {
compatible = "idt,5p49v6965";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x304_clk>;
clock-names = "xin";
/* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */
assigned-clocks = <&versaclock6_bb 1>,
<&versaclock6_bb 2>,
<&versaclock6_bb 3>,
<&versaclock6_bb 4>;
assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>;
};
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
};
&i2c5 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c5_pins>;
pinctrl-names = "default";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:Default */
0x0000 /* 3:Default */
0x0000 /* 4:Default */
0x0000 /* 5:Default */
>;
port {
wm8962_endpoint: endpoint {
remote-endpoint = <&rsnd_endpoint0>;
};
};
};
/* 0 - lcd_reset */
/* 1 - lcd_pwr */
/* 2 - lcd_select */
/* 3 - backlight-enable */
/* 4 - Touch_shdwn */
/* 5 - LCD_H_pol */
/* 6 - lcd_V_pol */
gpio_exp1: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
touchscreen@26 {
compatible = "ilitek,ili2117";
reg = <0x26>;
interrupt-parent = <&gpio5>;
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
wakeup-source;
};
hd3ss3220@47 {
compatible = "ti,hd3ss3220";
reg = <0x47>;
interrupt-parent = <&gpio6>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
hd3ss3220_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
&ohci1 {
status = "okay";
};
&pciec0 {
status = "okay";
};
&pciec1 {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pfc {
can0_pins: can0 {
groups = "can0_data_a";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data";
function = "can1";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_clk_out_1", "du_disp";
function = "du";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
i2c5_pins: i2c5 {
groups = "i2c5";
function = "i2c5";
};
led_pins: leds {
/* GP_0_4 , AVS1, AVS2, GP_7_3 */
pins = "GP_0_4", "GP_7_0", "GP_7_1", "GP_7_3";
bias-pull-down;
};
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
pwm2_pins: pwm2 {
groups = "pwm2_a";
function = "pwm2_a";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a";
function = "audio_clk";
};
usb0_pins: usb0 {
mux {
groups = "usb0";
function = "usb0";
};
};
usb1_pins: usb1 {
mux {
groups = "usb1";
function = "usb1";
};
};
usb30_pins: usb30 {
mux {
groups = "usb30";
function = "usb30";
};
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm2 {
pinctrl-0 = <&pwm2_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600>;
status = "okay";
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
<&cpg CPG_CORE R8A774A1_CLK_S0D4>;
ports {
#address-cells = <1>;
#size-cells = <0>;
rsnd_port0: port@0 {
reg = <0>;
rsnd_endpoint0: endpoint {
remote-endpoint = <&wm8962_endpoint>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint0>;
frame-master = <&rsnd_endpoint0>;
playback = <&ssi1 &dvc1 &src1>;
capture = <&ssi0>;
};
};
rsnd_port1: port@1 {
reg = <0x01>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
&rwdt {
status = "okay";
timeout-sec = <60>;
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif5 {
pinctrl-0 = <&scif5_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&ssi1 {
shared-pin;
};
&tmu0 {
status = "okay";
};
&tmu1 {
status = "okay";
};
&tmu2 {
status = "okay";
};
&tmu3 {
status = "okay";
};
&tmu4 {
status = "okay";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb3_peri0 {
companion = <&xhci0>;
status = "okay";
usb-role-switch;
port {
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_ep>;
};
};
};
&usb3_phy0 {
status = "okay";
};
&vin0 {
status = "okay";
};
&vin1 {
status = "okay";
};
&vin2 {
status = "okay";
};
&vin3 {
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&vin6 {
status = "okay";
};
&vin7 {
status = "okay";
};
&xhci0
{
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Compass Electronics Group, LLC
*/
#include <dt-bindings/gpio/gpio.h>
/ {
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
osc_32k: osc_32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "osc_32k";
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
wlan_pwrseq: wlan_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
clocks = <&osc_32k>;
clock-names = "ext_clock";
post-power-on-delay-ms = <80>;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gpio6 {
usb_hub_reset {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
max-speed = <4000000>;
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
clocks = <&osc_32k>;
clock-names = "extclk";
};
};
&hscif2 {
status = "okay";
pinctrl-0 = <&hscif2_pins>;
pinctrl-names = "default";
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
pca9654: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"i2c4_20_0",
"wl_reg_on",
"bt_reg_on",
"i2c4_20_3",
"i2c4_20_4",
"bt_dev_wake",
"i2c4_20_6",
"i2c4_20_7";
};
pca9654_lte: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
interrupt-parent = <&gpio5>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"i2c4_21_0",
"zoe_pwr_on",
"zoe_extint",
"zoe_reset_n",
"sara_reset",
"i2c4_21_5",
"sara_pwr_off",
"sara_networking_status";
};
eeprom@50 {
compatible = "microchip,at24c64", "atmel,24c64";
pagesize = <32>;
read-only; /* Manufacturing EEPROM programmed at factory */
reg = <0x50>;
};
rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
};
versaclock5: versaclock_som@6a {
compatible = "idt,5p49v6965";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x304_clk>;
clock-names = "xin";
/* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */
assigned-clocks = <&versaclock5 1>,
<&versaclock5 2>,
<&versaclock5 3>,
<&versaclock5 4>;
assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
};
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
mux {
groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb";
};
pins_mdio {
groups = "avb_mdio";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
hscif1_pins: hscif1 {
groups = "hscif1_data_a", "hscif1_ctrl_a";
function = "hscif1";
};
hscif2_pins: hscif2 {
groups = "hscif2_data_a";
function = "hscif2";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif5_pins: scif5 {
groups = "scif5_data_a";
function = "scif5";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
sdhi2_pins: sd2 {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
function = "sdhi3";
power-source = <1800>;
};
};
&scif_clk {
clock-frequency = <14745600>;
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi2 {
pinctrl-names = "default";
pinctrl-0 = <&sdhi2_pins>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
cap-power-off-card;
pm-ignore-notify;
keep-power-in-suspend;
mmc-pwrseq = <&wlan_pwrseq>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio1>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
&usb_extal_clk {
clock-frequency = <50000000>;
};
&usb3s0_clk {
clock-frequency = <100000000>;
};
&vspb {
status = "okay";
};
&vspi0 {
status = "okay";
};

1
arch/arm64/boot/dts/renesas/cat875.dtsi
View File

@ -18,7 +18,6 @@
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii";
status = "okay";
phy0: ethernet-phy@0 {

4
arch/arm64/boot/dts/renesas/hihope-common.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2[MN] main board
* Rev.[2.0/3.0/4.0] common parts
* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
* HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/

4
arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2[MN] Rev.3.0/4.0 main board
* common parts
* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
* HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/

2
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the RZ/G2[MN] HiHope sub board common parts
* Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/

29
arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts Normal file
View File

@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Compass Electronics Group, LLC
*/
/dts-v1/;
#include "r8a774a1.dtsi"
#include "beacon-renesom-som.dtsi"
#include "beacon-renesom-baseboard.dtsi"
/ {
model = "Beacon EmbeddedWorks RZ/G2M Development Kit";
compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
aliases {
serial0 = &scif2;
serial1 = &hscif0;
serial2 = &hscif1;
serial3 = &scif0;
serial4 = &hscif2;
serial5 = &scif5;
ethernet0 = &avb;
};
chosen {
stdout-path = "serial0:115200n8";
};
};

8
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -2252,7 +2252,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
@ -2264,7 +2264,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
@ -2276,7 +2276,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
@ -2288,7 +2288,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;

8
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@ -2110,7 +2110,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a774b1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
@ -2122,7 +2122,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a774b1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
@ -2134,7 +2134,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a774b1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
@ -2146,7 +2146,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a774b1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;

6
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@ -1618,7 +1618,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a774c0",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
@ -1630,7 +1630,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a774c0",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
@ -1642,7 +1642,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a774c0",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;

15
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H sub board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774e1-hihope-rzg2h.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2H with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
"renesas,r8a774e1";
};

26
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts Normal file
View File

@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H main board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774e1.dtsi"
#include "hihope-rev4.dtsi"
/ {
model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x80000000>;
};
};

1664
arch/arm64/boot/dts/renesas/r8a774e1.dtsi Normal file
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File diff suppressed because it is too large Load Diff

8
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View File

@ -2590,7 +2590,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
@ -2603,7 +2603,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
@ -2616,7 +2616,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
@ -2629,7 +2629,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;

8
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@ -2394,7 +2394,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
@ -2407,7 +2407,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
@ -2420,7 +2420,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
@ -2433,7 +2433,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;

8
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@ -1346,7 +1346,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a77961",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
@ -1358,7 +1358,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a77961",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
@ -1370,7 +1370,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77961",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
@ -1382,7 +1382,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a77961",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;

8
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@ -2120,7 +2120,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
@ -2133,7 +2133,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
@ -2146,7 +2146,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
@ -2159,7 +2159,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;

67
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
View File

@ -187,12 +187,79 @@
function = "i2c0";
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";

67
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
View File

@ -212,12 +212,79 @@
power-source = <3300>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";

17
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@ -1039,6 +1039,23 @@
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77970-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x4000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;

67
arch/arm64/boot/dts/renesas/r8a77980-condor.dts
View File

@ -262,6 +262,11 @@
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
@ -273,6 +278,68 @@
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";

67
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
View File

@ -187,6 +187,11 @@
function = "i2c0";
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
@ -198,6 +203,68 @@
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";

17
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@ -1344,6 +1344,23 @@
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77980-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x4000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;

1
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
View File

@ -715,6 +715,7 @@
mmc-hs400-1_8v;
bus-width = <8>;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};

6
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@ -1595,7 +1595,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a77990",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
@ -1608,7 +1608,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a77990",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
@ -1621,7 +1621,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a77990",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;

2
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View File

@ -916,7 +916,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77995",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;

1
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View File

@ -833,6 +833,7 @@
mmc-hs400-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
full-pwr-cycle-in-suspend;
status = "okay";
};

1
arch/arm64/configs/defconfig
View File

@ -865,6 +865,7 @@ CONFIG_QCOM_APR=m
CONFIG_ARCH_R8A774A1=y
CONFIG_ARCH_R8A774B1=y
CONFIG_ARCH_R8A774C0=y
CONFIG_ARCH_R8A774E1=y
CONFIG_ARCH_R8A77950=y
CONFIG_ARCH_R8A77951=y
CONFIG_ARCH_R8A77960=y

59
include/dt-bindings/clock/r8a774e1-cpg-mssr.h Normal file
View File

@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R8A774E1 CPG Core Clocks */
#define R8A774E1_CLK_Z 0
#define R8A774E1_CLK_Z2 1
#define R8A774E1_CLK_ZG 2
#define R8A774E1_CLK_ZTR 3
#define R8A774E1_CLK_ZTRD2 4
#define R8A774E1_CLK_ZT 5
#define R8A774E1_CLK_ZX 6
#define R8A774E1_CLK_S0D1 7
#define R8A774E1_CLK_S0D2 8
#define R8A774E1_CLK_S0D3 9
#define R8A774E1_CLK_S0D4 10
#define R8A774E1_CLK_S0D6 11
#define R8A774E1_CLK_S0D8 12
#define R8A774E1_CLK_S0D12 13
#define R8A774E1_CLK_S1D2 14
#define R8A774E1_CLK_S1D4 15
#define R8A774E1_CLK_S2D1 16
#define R8A774E1_CLK_S2D2 17
#define R8A774E1_CLK_S2D4 18
#define R8A774E1_CLK_S3D1 19
#define R8A774E1_CLK_S3D2 20
#define R8A774E1_CLK_S3D4 21
#define R8A774E1_CLK_LB 22
#define R8A774E1_CLK_CL 23
#define R8A774E1_CLK_ZB3 24
#define R8A774E1_CLK_ZB3D2 25
#define R8A774E1_CLK_ZB3D4 26
#define R8A774E1_CLK_CR 27
#define R8A774E1_CLK_CRD2 28
#define R8A774E1_CLK_SD0H 29
#define R8A774E1_CLK_SD0 30
#define R8A774E1_CLK_SD1H 31
#define R8A774E1_CLK_SD1 32
#define R8A774E1_CLK_SD2H 33
#define R8A774E1_CLK_SD2 34
#define R8A774E1_CLK_SD3H 35
#define R8A774E1_CLK_SD3 36
#define R8A774E1_CLK_RPC 37
#define R8A774E1_CLK_RPCD2 38
#define R8A774E1_CLK_MSO 39
#define R8A774E1_CLK_HDMI 40
#define R8A774E1_CLK_CSI0 41
#define R8A774E1_CLK_CP 42
#define R8A774E1_CLK_CPEX 43
#define R8A774E1_CLK_R 44
#define R8A774E1_CLK_OSC 45
#define R8A774E1_CLK_CANFD 46
#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */

36
include/dt-bindings/power/r8a774e1-sysc.h Normal file
View File

@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774E1_PD_CA57_CPU0 0
#define R8A774E1_PD_CA57_CPU1 1
#define R8A774E1_PD_CA57_CPU2 2
#define R8A774E1_PD_CA57_CPU3 3
#define R8A774E1_PD_CA53_CPU0 5
#define R8A774E1_PD_CA53_CPU1 6
#define R8A774E1_PD_CA53_CPU2 7
#define R8A774E1_PD_CA53_CPU3 8
#define R8A774E1_PD_A3VP 9
#define R8A774E1_PD_CA57_SCU 12
#define R8A774E1_PD_A3VC 14
#define R8A774E1_PD_3DG_A 17
#define R8A774E1_PD_3DG_B 18
#define R8A774E1_PD_3DG_C 19
#define R8A774E1_PD_3DG_D 20
#define R8A774E1_PD_CA53_SCU 21
#define R8A774E1_PD_3DG_E 22
#define R8A774E1_PD_A2VC1 26
/* Always-on power area */
#define R8A774E1_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */