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clk: socfpga: use clk_hw_register for a5/c5

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As recommended by Stephen Boyd, convert the cyclone5/arria5 clock driver
to use the clk_hw registration method.

Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210302214151.1333447-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Dinh Nguyen 2021-03-02 15:41:49 -06:00 committed by Stephen Boyd
parent a38fd87484
commit 2c2b9c6067
3 changed files with 22 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/clk/socfpga/clk-gate.c
View File

@ -174,13 +174,14 @@ void __init socfpga_gate_init(struct device_node *node)
u32 div_reg[3];
u32 clk_phase[2];
u32 fixed_div;
struct clk *clk;
struct clk_hw *hw_clk;
struct socfpga_gate_clk *socfpga_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct clk_ops *ops;
int rc;
int err;
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
if (WARN_ON(!socfpga_clk))
@ -238,12 +239,14 @@ void __init socfpga_gate_init(struct device_node *node)
init.parent_names = parent_name;
socfpga_clk->hw.hw.init = &init;
clk = clk_register(NULL, &socfpga_clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
hw_clk = &socfpga_clk->hw.hw;
err = clk_hw_register(NULL, hw_clk);
if (err) {
kfree(socfpga_clk);
return;
}
rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
if (WARN_ON(rc))
return;
}

8
drivers/clk/socfpga/clk-periph.c
View File

@ -51,7 +51,7 @@ static __init void __socfpga_periph_init(struct device_node *node,
const struct clk_ops *ops)
{
u32 reg;
struct clk *clk;
struct clk_hw *hw_clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
@ -94,13 +94,13 @@ static __init void __socfpga_periph_init(struct device_node *node,
init.parent_names = parent_name;
periph_clk->hw.hw.init = &init;
hw_clk = &periph_clk->hw.hw;
clk = clk_register(NULL, &periph_clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
if (clk_hw_register(NULL, hw_clk)) {
kfree(periph_clk);
return;
}
rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
}
void __init socfpga_periph_init(struct device_node *node)

18
drivers/clk/socfpga/clk-pll.c
View File

@ -70,16 +70,18 @@ static const struct clk_ops clk_pll_ops = {
.get_parent = clk_pll_get_parent,
};
static __init struct clk *__socfpga_pll_init(struct device_node *node,
static __init struct clk_hw *__socfpga_pll_init(struct device_node *node,
const struct clk_ops *ops)
{
u32 reg;
struct clk *clk;
struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct device_node *clkmgr_np;
int rc;
int err;
of_property_read_u32(node, "reg", &reg);
@ -105,13 +107,15 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
clk = clk_register(NULL, &pll_clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
hw_clk = &pll_clk->hw.hw;
err = clk_hw_register(NULL, hw_clk);
if (err) {
kfree(pll_clk);
return NULL;
return ERR_PTR(err);
}
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return clk;
rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
return hw_clk;
}
void __init socfpga_pll_init(struct device_node *node)