riscv: dts: sophgo: add Huashan Pi board device tree
Add initial device tree files for the Huashan Pi board. Note: The boot of CV1812H chip needs a rtos firmware for coprocessor to function properly. To make the soc happy, reserved the last 2M memory for the rtos firmware. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://en.sophgo.com/product/introduce/huashan.html Link: https://en.sophgo.com/product/introduce/cv181xH.html Link: https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/build/boards/cv181x/cv1812h_wevb_0007a_emmc_huashan/memmap.py#L15 Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
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dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
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dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
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arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
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arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
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*/
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/dts-v1/;
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#include "cv1812h.dtsi"
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/ {
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model = "Huashan Pi";
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compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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coprocessor_rtos: region@8fe00000 {
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reg = <0x8fe00000 0x200000>;
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no-map;
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};
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};
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};
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&osc {
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clock-frequency = <25000000>;
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};
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&uart0 {
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status = "okay";
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};
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