powerpc/powernv/pci: Introduce __pnv_pci_ioda_msi_setup()
It will be used as a 'compose_msg' handler of the MSI domain introduced later. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210701132750.1475580-12-clg@kaod.org
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@ -2016,15 +2016,17 @@ bool is_pnv_opal_msi(struct irq_chip *chip)
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}
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EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
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static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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unsigned int hwirq, unsigned int virq,
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unsigned int is_64, struct msi_msg *msg)
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static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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unsigned int xive_num,
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unsigned int is_64, struct msi_msg *msg)
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{
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struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
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unsigned int xive_num = hwirq - phb->msi_base;
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__be32 data;
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int rc;
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dev_dbg(&dev->dev, "%s: setup %s-bit MSI for vector #%d\n", __func__,
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is_64 ? "64" : "32", xive_num);
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/* No PE assigned ? bail out ... no MSI for you ! */
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if (pe == NULL)
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return -ENXIO;
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@ -2072,12 +2074,28 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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}
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msg->data = be32_to_cpu(data);
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return 0;
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}
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static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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unsigned int hwirq, unsigned int virq,
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unsigned int is_64, struct msi_msg *msg)
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{
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struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
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unsigned int xive_num = hwirq - phb->msi_base;
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int rc;
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rc = __pnv_pci_ioda_msi_setup(phb, dev, xive_num, is_64, msg);
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if (rc)
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return rc;
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/* P8 only */
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pnv_set_msi_irq_chip(phb, virq);
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pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
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" address=%x_%08x data=%x PE# %x\n",
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pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
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msg->address_hi, msg->address_lo, data, pe->pe_number);
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msg->address_hi, msg->address_lo, msg->data, pe->pe_number);
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return 0;
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}
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