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Merge branch 'for-linus' of git://gitorious.org/linux-omap-dss2/linux

Browse Source 
* 'for-linus' of git://gitorious.org/linux-omap-dss2/linux:
  OMAP: DSS2: don't power off a panel twice
  OMAP: DSS2: OMAPFB: Allow usage of def_vrfb only for omap2,3
  OMAP: DSS2: OMAPFB: make VRFB depends on OMAP2,3
  OMAP: DSS2: OMAPFB: Allow FB_OMAP2 to build without VRFB
  arm/omap: simplify conditional
  OMAP: DSS2: DSI: Remove extra iounmap in error path
  OMAP: DSS2: Use dss_features framework on DSS2 code
  OMAP: DSS2: Introduce dss_features files
  video/omap: remove mux.h include
  ARM: omap/fb: move get_fbmem_region() to .init.text
  ARM: omap/fb: move omapfb_reserve_sram to .init.text
  ARM: omap/fb: move omap_init_fb to .init.text
  OMAP: DSS2: OMAPFB: swap front and back porches for both hsync and vsync
  OMAP: DSS2: make filter coefficient tables human readable
  OMAP: DSS2: Add SPI dependency to Kconfig of ACX565AKM panel
This commit is contained in:
Linus Torvalds 2010-10-26 10:02:39 -07:00
commit 2c518959f0
21 changed files with 478 additions and 231 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm/plat-omap/fb.c
View File

@ -96,7 +96,7 @@ static int fbmem_region_reserved(unsigned long start, size_t size)
* Get the region_idx`th region from board config/ATAG and convert it to
* our internal format.
*/
static int get_fbmem_region(int region_idx, struct omapfb_mem_region *rg)
static int __init get_fbmem_region(int region_idx, struct omapfb_mem_region *rg)
{
const struct omap_fbmem_config *conf;
u32 paddr;
@ -128,7 +128,7 @@ static int set_fbmem_region_type(struct omapfb_mem_region *rg, int mem_type,
* type = 0 && paddr = 0, a default don't care case maps to
* the SDRAM type.
*/
if (rg->type || (!rg->type && !rg->paddr))
if (rg->type || !rg->paddr)
return 0;
if (ranges_overlap(rg->paddr, rg->size, mem_start, mem_size)) {
rg->type = mem_type;
@ -260,7 +260,7 @@ void __init omapfb_reserve_sdram_memblock(void)
* this point, since the driver built as a module would have problem with
* freeing / reallocating the regions.
*/
unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
unsigned long sram_vstart,
unsigned long sram_size,
unsigned long pstart_avail,
@ -334,7 +334,7 @@ void omapfb_set_ctrl_platform_data(void *data)
omapfb_config.ctrl_platform_data = data;
}
static inline int omap_init_fb(void)
static int __init omap_init_fb(void)
{
const struct omap_lcd_config *conf;
@ -379,7 +379,7 @@ void omapfb_set_platform_data(struct omapfb_platform_data *data)
omapfb_config = *data;
}
static inline int omap_init_fb(void)
static int __init omap_init_fb(void)
{
return platform_device_register(&omap_fb_device);
}
@ -390,7 +390,7 @@ void omapfb_reserve_sdram_memblock(void)
{
}
unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
unsigned long sram_vstart,
unsigned long sram_size,
unsigned long start_avail,
@ -409,7 +409,7 @@ void omapfb_reserve_sdram_memblock(void)
{
}
unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
unsigned long sram_vstart,
unsigned long sram_size,
unsigned long start_avail,

31
arch/arm/plat-omap/include/plat/display.h
View File

@ -81,37 +81,6 @@ enum omap_color_mode {
OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
OMAP_DSS_COLOR_GFX_OMAP2 =
OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
OMAP_DSS_COLOR_VID_OMAP2 =
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
OMAP_DSS_COLOR_UYVY,
OMAP_DSS_COLOR_GFX_OMAP3 =
OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
OMAP_DSS_COLOR_VID1_OMAP3 =
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
OMAP_DSS_COLOR_VID2_OMAP3 =
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
};
enum omap_lcd_display_type {

16
arch/arm/plat-omap/include/plat/vrfb.h
View File

@ -35,6 +35,7 @@ struct vrfb {
bool yuv_mode;
};
#ifdef CONFIG_OMAP2_VRFB
extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
@ -47,4 +48,19 @@ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
extern void omap_vrfb_restore_context(void);
#else
static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; }
static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {}
static inline void omap_vrfb_adjust_size(u16 *width, u16 *height,
u8 bytespp) {}
static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp)
{ return 0; }
static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp)
{ return 0; }
static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
u16 width, u16 height, unsigned bytespp, bool yuv_mode) {}
static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot)
{ return 0; }
static inline void omap_vrfb_restore_context(void) {}
#endif
#endif /* __VRFB_H */

2
drivers/video/omap/lcd_omap3beagle.c
View File

@ -25,8 +25,6 @@
#include <linux/gpio.h>
#include <linux/i2c/twl.h>
#include <plat/mux.h>
#include <plat/mux.h>
#include <asm/mach-types.h>
#include "omapfb.h"

2
drivers/video/omap2/displays/Kconfig
View File

@ -40,7 +40,7 @@ config PANEL_TPO_TD043MTEA1
config PANEL_ACX565AKM
tristate "ACX565AKM Panel"
depends on OMAP2_DSS_SDI
depends on OMAP2_DSS_SDI && SPI
select BACKLIGHT_CLASS_DEVICE
help
This is the LCD panel used on Nokia N900

6
drivers/video/omap2/displays/panel-acx565akm.c
View File

@ -587,6 +587,9 @@ static int acx_panel_power_on(struct omap_dss_device *dssdev)
dev_dbg(&dssdev->dev, "%s\n", __func__);
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
return 0;
mutex_lock(&md->mutex);
r = omapdss_sdi_display_enable(dssdev);
@ -644,6 +647,9 @@ static void acx_panel_power_off(struct omap_dss_device *dssdev)
dev_dbg(&dssdev->dev, "%s\n", __func__);
if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
return;
mutex_lock(&md->mutex);
if (!md->enabled) {

6
drivers/video/omap2/displays/panel-generic.c
View File

@ -39,6 +39,9 @@ static int generic_panel_power_on(struct omap_dss_device *dssdev)
{
int r;
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
return 0;
r = omapdss_dpi_display_enable(dssdev);
if (r)
goto err0;
@ -58,6 +61,9 @@ err0:
static void generic_panel_power_off(struct omap_dss_device *dssdev)
{
if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
return;
if (dssdev->platform_disable)
dssdev->platform_disable(dssdev);

6
drivers/video/omap2/displays/panel-sharp-lq043t1dg01.c
View File

@ -43,6 +43,9 @@ static int sharp_lq_panel_power_on(struct omap_dss_device *dssdev)
{
int r;
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
return 0;
r = omapdss_dpi_display_enable(dssdev);
if (r)
goto err0;
@ -65,6 +68,9 @@ err0:
static void sharp_lq_panel_power_off(struct omap_dss_device *dssdev)
{
if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
return;
if (dssdev->platform_disable)
dssdev->platform_disable(dssdev);

6
drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
View File

@ -135,6 +135,9 @@ static int sharp_ls_power_on(struct omap_dss_device *dssdev)
{
int r = 0;
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
return 0;
r = omapdss_dpi_display_enable(dssdev);
if (r)
goto err0;
@ -157,6 +160,9 @@ err0:
static void sharp_ls_power_off(struct omap_dss_device *dssdev)
{
if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
return;
if (dssdev->platform_disable)
dssdev->platform_disable(dssdev);

6
drivers/video/omap2/displays/panel-toppoly-tdo35s.c
View File

@ -46,6 +46,9 @@ static int toppoly_tdo_panel_power_on(struct omap_dss_device *dssdev)
{
int r;
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
return 0;
r = omapdss_dpi_display_enable(dssdev);
if (r)
goto err0;
@ -65,6 +68,9 @@ err0:
static void toppoly_tdo_panel_power_off(struct omap_dss_device *dssdev)
{
if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
return;
if (dssdev->platform_disable)
dssdev->platform_disable(dssdev);

6
drivers/video/omap2/displays/panel-tpo-td043mtea1.c
View File

@ -269,6 +269,9 @@ static int tpo_td043_power_on(struct omap_dss_device *dssdev)
int nreset_gpio = dssdev->reset_gpio;
int r;
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
return 0;
r = omapdss_dpi_display_enable(dssdev);
if (r)
goto err0;
@ -308,6 +311,9 @@ static void tpo_td043_power_off(struct omap_dss_device *dssdev)
struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
int nreset_gpio = dssdev->reset_gpio;
if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
return;
tpo_td043_write(tpo_td043->spi, 3,
TPO_R03_VAL_STANDBY | TPO_R03_EN_PWM);

2
drivers/video/omap2/dss/Makefile
View File

@ -1,5 +1,5 @@
obj-$(CONFIG_OMAP2_DSS) += omapdss.o
omapdss-y := core.o dss.o dispc.o display.o manager.o overlay.o
omapdss-y := core.o dss.o dss_features.o dispc.o display.o manager.o overlay.o
omapdss-$(CONFIG_OMAP2_DSS_DPI) += dpi.o
omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o

3
drivers/video/omap2/dss/core.c
View File

@ -37,6 +37,7 @@
#include <plat/clock.h>
#include "dss.h"
#include "dss_features.h"
static struct {
struct platform_device *pdev;
@ -502,6 +503,8 @@ static int omap_dss_probe(struct platform_device *pdev)
core.pdev = pdev;
dss_features_init();
dss_init_overlay_managers(pdev);
dss_init_overlays(pdev);

276
drivers/video/omap2/dss/dispc.c
View File

@ -39,6 +39,7 @@
#include <plat/display.h>
#include "dss.h"
#include "dss_features.h"
/* DISPC */
#define DISPC_BASE 0x48050400
@ -139,6 +140,22 @@ struct omap_dispc_isr_data {
u32 mask;
};
struct dispc_h_coef {
s8 hc4;
s8 hc3;
u8 hc2;
s8 hc1;
s8 hc0;
};
struct dispc_v_coef {
s8 vc22;
s8 vc2;
u8 vc1;
s8 vc0;
s8 vc00;
};
#define REG_GET(idx, start, end) \
FLD_GET(dispc_read_reg(idx), start, end)
@ -564,106 +581,77 @@ static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
int vscaleup, int five_taps)
{
/* Coefficients for horizontal up-sampling */
static const u32 coef_hup[8] = {
0x00800000,
0x0D7CF800,
0x1E70F5FF,
0x335FF5FE,
0xF74949F7,
0xF55F33FB,
0xF5701EFE,
0xF87C0DFF,
};
/* Coefficients for horizontal down-sampling */
static const u32 coef_hdown[8] = {
0x24382400,
0x28371FFE,
0x2C361BFB,
0x303516F9,
0x11343311,
0x1635300C,
0x1B362C08,
0x1F372804,
};
/* Coefficients for horizontal and vertical up-sampling */
static const u32 coef_hvup[2][8] = {
{
0x00800000,
0x037B02FF,
0x0C6F05FE,
0x205907FB,
0x00404000,
0x075920FE,
0x056F0CFF,
0x027B0300,
},
{
0x00800000,
0x0D7CF8FF,
0x1E70F5FE,
0x335FF5FB,
0xF7404000,
0xF55F33FE,
0xF5701EFF,
0xF87C0D00,
},
};
/* Coefficients for horizontal and vertical down-sampling */
static const u32 coef_hvdown[2][8] = {
{
0x24382400,
0x28391F04,
0x2D381B08,
0x3237170C,
0x123737F7,
0x173732F9,
0x1B382DFB,
0x1F3928FE,
},
{
0x24382400,
0x28371F04,
0x2C361B08,
0x3035160C,
0x113433F7,
0x163530F9,
0x1B362CFB,
0x1F3728FE,
},
static const struct dispc_h_coef coef_hup[8] = {
{ 0, 0, 128, 0, 0 },
{ -1, 13, 124, -8, 0 },
{ -2, 30, 112, -11, -1 },
{ -5, 51, 95, -11, -2 },
{ 0, -9, 73, 73, -9 },
{ -2, -11, 95, 51, -5 },
{ -1, -11, 112, 30, -2 },
{ 0, -8, 124, 13, -1 },
};
/* Coefficients for vertical up-sampling */
static const u32 coef_vup[8] = {
0x00000000,
0x0000FF00,
0x0000FEFF,
0x0000FBFE,
0x000000F7,
0x0000FEFB,
0x0000FFFE,
0x000000FF,
static const struct dispc_v_coef coef_vup_3tap[8] = {
{ 0, 0, 128, 0, 0 },
{ 0, 3, 123, 2, 0 },
{ 0, 12, 111, 5, 0 },
{ 0, 32, 89, 7, 0 },
{ 0, 0, 64, 64, 0 },
{ 0, 7, 89, 32, 0 },
{ 0, 5, 111, 12, 0 },
{ 0, 2, 123, 3, 0 },
};
static const struct dispc_v_coef coef_vup_5tap[8] = {
{ 0, 0, 128, 0, 0 },
{ -1, 13, 124, -8, 0 },
{ -2, 30, 112, -11, -1 },
{ -5, 51, 95, -11, -2 },
{ 0, -9, 73, 73, -9 },
{ -2, -11, 95, 51, -5 },
{ -1, -11, 112, 30, -2 },
{ 0, -8, 124, 13, -1 },
};
/* Coefficients for horizontal down-sampling */
static const struct dispc_h_coef coef_hdown[8] = {
{ 0, 36, 56, 36, 0 },
{ 4, 40, 55, 31, -2 },
{ 8, 44, 54, 27, -5 },
{ 12, 48, 53, 22, -7 },
{ -9, 17, 52, 51, 17 },
{ -7, 22, 53, 48, 12 },
{ -5, 27, 54, 44, 8 },
{ -2, 31, 55, 40, 4 },
};
/* Coefficients for vertical down-sampling */
static const u32 coef_vdown[8] = {
0x00000000,
0x000004FE,
0x000008FB,
0x00000CF9,
0x0000F711,
0x0000F90C,
0x0000FB08,
0x0000FE04,
static const struct dispc_v_coef coef_vdown_3tap[8] = {
{ 0, 36, 56, 36, 0 },
{ 0, 40, 57, 31, 0 },
{ 0, 45, 56, 27, 0 },
{ 0, 50, 55, 23, 0 },
{ 0, 18, 55, 55, 0 },
{ 0, 23, 55, 50, 0 },
{ 0, 27, 56, 45, 0 },
{ 0, 31, 57, 40, 0 },
};
const u32 *h_coef;
const u32 *hv_coef;
const u32 *hv_coef_mod;
const u32 *v_coef;
static const struct dispc_v_coef coef_vdown_5tap[8] = {
{ 0, 36, 56, 36, 0 },
{ 4, 40, 55, 31, -2 },
{ 8, 44, 54, 27, -5 },
{ 12, 48, 53, 22, -7 },
{ -9, 17, 52, 51, 17 },
{ -7, 22, 53, 48, 12 },
{ -5, 27, 54, 44, 8 },
{ -2, 31, 55, 40, 4 },
};
const struct dispc_h_coef *h_coef;
const struct dispc_v_coef *v_coef;
int i;
if (hscaleup)
@ -671,47 +659,34 @@ static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
else
h_coef = coef_hdown;
if (vscaleup) {
hv_coef = coef_hvup[five_taps];
v_coef = coef_vup;
if (hscaleup)
hv_coef_mod = NULL;
else
hv_coef_mod = coef_hvdown[five_taps];
} else {
hv_coef = coef_hvdown[five_taps];
v_coef = coef_vdown;
if (hscaleup)
hv_coef_mod = coef_hvup[five_taps];
else
hv_coef_mod = NULL;
}
if (vscaleup)
v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
else
v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
for (i = 0; i < 8; i++) {
u32 h, hv;
h = h_coef[i];
hv = hv_coef[i];
if (hv_coef_mod) {
hv &= 0xffffff00;
hv |= (hv_coef_mod[i] & 0xff);
}
h = FLD_VAL(h_coef[i].hc0, 7, 0)
| FLD_VAL(h_coef[i].hc1, 15, 8)
| FLD_VAL(h_coef[i].hc2, 23, 16)
| FLD_VAL(h_coef[i].hc3, 31, 24);
hv = FLD_VAL(h_coef[i].hc4, 7, 0)
| FLD_VAL(v_coef[i].vc0, 15, 8)
| FLD_VAL(v_coef[i].vc1, 23, 16)
| FLD_VAL(v_coef[i].vc2, 31, 24);
_dispc_write_firh_reg(plane, i, h);
_dispc_write_firhv_reg(plane, i, hv);
}
if (!five_taps)
return;
for (i = 0; i < 8; i++) {
u32 v;
v = v_coef[i];
_dispc_write_firv_reg(plane, i, v);
if (five_taps) {
for (i = 0; i < 8; i++) {
u32 v;
v = FLD_VAL(v_coef[i].vc00, 7, 0)
| FLD_VAL(v_coef[i].vc22, 15, 8);
_dispc_write_firv_reg(plane, i, v);
}
}
}
@ -800,12 +775,12 @@ static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
{
BUG_ON(plane == OMAP_DSS_VIDEO1);
if (cpu_is_omap24xx())
if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
return;
BUG_ON(!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
plane == OMAP_DSS_VIDEO1);
if (plane == OMAP_DSS_GFX)
REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
else if (plane == OMAP_DSS_VIDEO2)
@ -975,17 +950,14 @@ static void dispc_read_plane_fifo_sizes(void)
DISPC_VID_FIFO_SIZE_STATUS(1) };
u32 size;
int plane;
u8 start, end;
enable_clocks(1);
for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
if (cpu_is_omap24xx())
size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
else if (cpu_is_omap34xx())
size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
else
BUG();
dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
dispc.fifo_size[plane] = size;
}
@ -1002,6 +974,8 @@ void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
DISPC_VID_FIFO_THRESHOLD(0),
DISPC_VID_FIFO_THRESHOLD(1) };
u8 hi_start, hi_end, lo_start, lo_end;
enable_clocks(1);
DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
@ -1010,12 +984,12 @@ void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
REG_GET(ftrs_reg[plane], 27, 16),
low, high);
if (cpu_is_omap24xx())
dispc_write_reg(ftrs_reg[plane],
FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
else
dispc_write_reg(ftrs_reg[plane],
FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
dispc_write_reg(ftrs_reg[plane],
FLD_VAL(high, hi_start, hi_end) |
FLD_VAL(low, lo_start, lo_end));
enable_clocks(0);
}
@ -1035,13 +1009,16 @@ static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
u32 val;
const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
DISPC_VID_FIR(1) };
u8 hinc_start, hinc_end, vinc_start, vinc_end;
BUG_ON(plane == OMAP_DSS_GFX);
if (cpu_is_omap24xx())
val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
else
val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
val = FLD_VAL(vinc, vinc_start, vinc_end) |
FLD_VAL(hinc, hinc_start, hinc_end);
dispc_write_reg(fir_reg[plane-1], val);
}
@ -1567,6 +1544,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
case OMAP_DSS_COLOR_ARGB16:
case OMAP_DSS_COLOR_ARGB32:
case OMAP_DSS_COLOR_RGBA32:
if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
return -EINVAL;
case OMAP_DSS_COLOR_RGBX32:
if (cpu_is_omap24xx())
return -EINVAL;
@ -1607,9 +1586,10 @@ static int _dispc_setup_plane(enum omap_plane plane,
case OMAP_DSS_COLOR_ARGB16:
case OMAP_DSS_COLOR_ARGB32:
case OMAP_DSS_COLOR_RGBA32:
if (cpu_is_omap24xx())
if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
return -EINVAL;
if (plane == OMAP_DSS_VIDEO1)
if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
plane == OMAP_DSS_VIDEO1)
return -EINVAL;
break;
@ -2002,7 +1982,7 @@ void dispc_enable_trans_key(enum omap_channel ch, bool enable)
}
void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
{
if (cpu_is_omap24xx())
if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
return;
enable_clocks(1);
@ -2016,7 +1996,7 @@ bool dispc_alpha_blending_enabled(enum omap_channel ch)
{
bool enabled;
if (cpu_is_omap24xx())
if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
return false;
enable_clocks(1);

1
drivers/video/omap2/dss/dsi.c
View File

@ -3274,7 +3274,6 @@ int dsi_init(struct platform_device *pdev)
dsi.vdds_dsi_reg = dss_get_vdds_dsi();
if (IS_ERR(dsi.vdds_dsi_reg)) {
iounmap(dsi.base);
DSSERR("can't get VDDS_DSI regulator\n");
r = PTR_ERR(dsi.vdds_dsi_reg);
goto err2;

191
drivers/video/omap2/dss/dss_features.c Normal file
View File

@ -0,0 +1,191 @@
/*
* linux/drivers/video/omap2/dss/dss_features.c
*
* Copyright (C) 2010 Texas Instruments
* Author: Archit Taneja <archit@ti.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <plat/display.h>
#include <plat/cpu.h>
#include "dss_features.h"
/* Defines a generic omap register field */
struct dss_reg_field {
enum dss_feat_reg_field id;
u8 start, end;
};
struct omap_dss_features {
const struct dss_reg_field *reg_fields;
const int num_reg_fields;
const u32 has_feature;
const int num_mgrs;
const int num_ovls;
const enum omap_display_type *supported_displays;
const enum omap_color_mode *supported_color_modes;
};
/* This struct is assigned to one of the below during initialization */
static struct omap_dss_features *omap_current_dss_features;
static const struct dss_reg_field omap2_dss_reg_fields[] = {
{ FEAT_REG_FIRHINC, 11, 0 },
{ FEAT_REG_FIRVINC, 27, 16 },
{ FEAT_REG_FIFOLOWTHRESHOLD, 8, 0 },
{ FEAT_REG_FIFOHIGHTHRESHOLD, 24, 16 },
{ FEAT_REG_FIFOSIZE, 8, 0 },
};
static const struct dss_reg_field omap3_dss_reg_fields[] = {
{ FEAT_REG_FIRHINC, 12, 0 },
{ FEAT_REG_FIRVINC, 28, 16 },
{ FEAT_REG_FIFOLOWTHRESHOLD, 11, 0 },
{ FEAT_REG_FIFOHIGHTHRESHOLD, 27, 16 },
{ FEAT_REG_FIFOSIZE, 10, 0 },
};
static const enum omap_display_type omap2_dss_supported_displays[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DISPLAY_TYPE_VENC,
};
static const enum omap_display_type omap3_dss_supported_displays[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DISPLAY_TYPE_VENC,
};
static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
/* OMAP_DSS_GFX */
OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
/* OMAP_DSS_VIDEO1 */
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
OMAP_DSS_COLOR_UYVY,
/* OMAP_DSS_VIDEO2 */
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
OMAP_DSS_COLOR_UYVY,
};
static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
/* OMAP_DSS_GFX */
OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
/* OMAP_DSS_VIDEO1 */
OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
/* OMAP_DSS_VIDEO2 */
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
};
/* OMAP2 DSS Features */
static struct omap_dss_features omap2_dss_features = {
.reg_fields = omap2_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
.num_mgrs = 2,
.num_ovls = 3,
.supported_displays = omap2_dss_supported_displays,
.supported_color_modes = omap2_dss_supported_color_modes,
};
/* OMAP3 DSS Features */
static struct omap_dss_features omap3_dss_features = {
.reg_fields = omap3_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
.has_feature = FEAT_GLOBAL_ALPHA,
.num_mgrs = 2,
.num_ovls = 3,
.supported_displays = omap3_dss_supported_displays,
.supported_color_modes = omap3_dss_supported_color_modes,
};
/* Functions returning values related to a DSS feature */
int dss_feat_get_num_mgrs(void)
{
return omap_current_dss_features->num_mgrs;
}
int dss_feat_get_num_ovls(void)
{
return omap_current_dss_features->num_ovls;
}
enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
{
return omap_current_dss_features->supported_displays[channel];
}
enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
{
return omap_current_dss_features->supported_color_modes[plane];
}
/* DSS has_feature check */
bool dss_has_feature(enum dss_feat_id id)
{
return omap_current_dss_features->has_feature & id;
}
void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
{
if (id >= omap_current_dss_features->num_reg_fields)
BUG();
*start = omap_current_dss_features->reg_fields[id].start;
*end = omap_current_dss_features->reg_fields[id].end;
}
void dss_features_init(void)
{
if (cpu_is_omap24xx())
omap_current_dss_features = &omap2_dss_features;
else
omap_current_dss_features = &omap3_dss_features;
}

50
drivers/video/omap2/dss/dss_features.h Normal file
View File

@ -0,0 +1,50 @@
/*
* linux/drivers/video/omap2/dss/dss_features.h
*
* Copyright (C) 2010 Texas Instruments
* Author: Archit Taneja <archit@ti.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __OMAP2_DSS_FEATURES_H
#define __OMAP2_DSS_FEATURES_H
#define MAX_DSS_MANAGERS 2
#define MAX_DSS_OVERLAYS 3
/* DSS has feature id */
enum dss_feat_id {
FEAT_GLOBAL_ALPHA = 1 << 0,
FEAT_GLOBAL_ALPHA_VID1 = 1 << 1,
};
/* DSS register field id */
enum dss_feat_reg_field {
FEAT_REG_FIRHINC,
FEAT_REG_FIRVINC,
FEAT_REG_FIFOHIGHTHRESHOLD,
FEAT_REG_FIFOLOWTHRESHOLD,
FEAT_REG_FIFOSIZE,
};
/* DSS Feature Functions */
int dss_feat_get_num_mgrs(void);
int dss_feat_get_num_ovls(void);
enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
bool dss_has_feature(enum dss_feat_id id);
void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end);
void dss_features_init(void);
#endif

33
drivers/video/omap2/dss/manager.c
View File

@ -33,6 +33,7 @@
#include <plat/cpu.h>
#include "dss.h"
#include "dss_features.h"
static int num_managers;
static struct list_head manager_list;
@ -448,8 +449,8 @@ struct manager_cache_data {
static struct {
spinlock_t lock;
struct overlay_cache_data overlay_cache[3];
struct manager_cache_data manager_cache[2];
struct overlay_cache_data overlay_cache[MAX_DSS_OVERLAYS];
struct manager_cache_data manager_cache[MAX_DSS_MANAGERS];
bool irq_enabled;
} dss_cache;
@ -882,12 +883,12 @@ static int configure_dispc(void)
{
struct overlay_cache_data *oc;
struct manager_cache_data *mc;
const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
const int num_ovls = dss_feat_get_num_ovls();
const int num_mgrs = dss_feat_get_num_mgrs();
int i;
int r;
bool mgr_busy[2];
bool mgr_go[2];
bool mgr_busy[MAX_DSS_MANAGERS];
bool mgr_go[MAX_DSS_MANAGERS];
bool busy;
r = 0;
@ -989,7 +990,7 @@ void dss_setup_partial_planes(struct omap_dss_device *dssdev,
{
struct overlay_cache_data *oc;
struct manager_cache_data *mc;
const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
const int num_ovls = dss_feat_get_num_ovls();
struct omap_overlay_manager *mgr;
int i;
u16 x, y, w, h;
@ -1121,8 +1122,8 @@ void dss_start_update(struct omap_dss_device *dssdev)
{
struct manager_cache_data *mc;
struct overlay_cache_data *oc;
const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
const int num_ovls = dss_feat_get_num_ovls();
const int num_mgrs = dss_feat_get_num_mgrs();
struct omap_overlay_manager *mgr;
int i;
@ -1151,10 +1152,10 @@ static void dss_apply_irq_handler(void *data, u32 mask)
{
struct manager_cache_data *mc;
struct overlay_cache_data *oc;
const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
const int num_ovls = dss_feat_get_num_ovls();
const int num_mgrs = dss_feat_get_num_mgrs();
int i, r;
bool mgr_busy[2];
bool mgr_busy[MAX_DSS_MANAGERS];
mgr_busy[0] = dispc_go_busy(0);
mgr_busy[1] = dispc_go_busy(1);
@ -1461,7 +1462,7 @@ int dss_init_overlay_managers(struct platform_device *pdev)
num_managers = 0;
for (i = 0; i < 2; ++i) {
for (i = 0; i < dss_feat_get_num_mgrs(); ++i) {
struct omap_overlay_manager *mgr;
mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
@ -1471,14 +1472,10 @@ int dss_init_overlay_managers(struct platform_device *pdev)
case 0:
mgr->name = "lcd";
mgr->id = OMAP_DSS_CHANNEL_LCD;
mgr->supported_displays =
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI;
break;
case 1:
mgr->name = "tv";
mgr->id = OMAP_DSS_CHANNEL_DIGIT;
mgr->supported_displays = OMAP_DISPLAY_TYPE_VENC;
break;
}
@ -1494,6 +1491,8 @@ int dss_init_overlay_managers(struct platform_device *pdev)
mgr->disable = &dss_mgr_disable;
mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC;
mgr->supported_displays =
dss_feat_get_supported_displays(mgr->id);
dss_overlay_setup_dispc_manager(mgr);

24
drivers/video/omap2/dss/overlay.c
View File

@ -35,6 +35,7 @@
#include <plat/cpu.h>
#include "dss.h"
#include "dss_features.h"
static int num_overlays;
static struct list_head overlay_list;
@ -237,7 +238,8 @@ static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl,
/* Video1 plane does not support global alpha
* to always make it 255 completely opaque
*/
if (ovl->id == OMAP_DSS_VIDEO1)
if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
ovl->id == OMAP_DSS_VIDEO1)
info.global_alpha = 255;
else
info.global_alpha = simple_strtoul(buf, NULL, 10);
@ -510,11 +512,11 @@ static void omap_dss_add_overlay(struct omap_overlay *overlay)
list_add_tail(&overlay->list, &overlay_list);
}
static struct omap_overlay *dispc_overlays[3];
static struct omap_overlay *dispc_overlays[MAX_DSS_OVERLAYS];
void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr)
{
mgr->num_overlays = 3;
mgr->num_overlays = dss_feat_get_num_ovls();
mgr->overlays = dispc_overlays;
}
@ -535,7 +537,7 @@ void dss_init_overlays(struct platform_device *pdev)
num_overlays = 0;
for (i = 0; i < 3; ++i) {
for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
struct omap_overlay *ovl;
ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
@ -545,18 +547,12 @@ void dss_init_overlays(struct platform_device *pdev)
case 0:
ovl->name = "gfx";
ovl->id = OMAP_DSS_GFX;
ovl->supported_modes = cpu_is_omap34xx() ?
OMAP_DSS_COLOR_GFX_OMAP3 :
OMAP_DSS_COLOR_GFX_OMAP2;
ovl->caps = OMAP_DSS_OVL_CAP_DISPC;
ovl->info.global_alpha = 255;
break;
case 1:
ovl->name = "vid1";
ovl->id = OMAP_DSS_VIDEO1;
ovl->supported_modes = cpu_is_omap34xx() ?
OMAP_DSS_COLOR_VID1_OMAP3 :
OMAP_DSS_COLOR_VID_OMAP2;
ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
OMAP_DSS_OVL_CAP_DISPC;
ovl->info.global_alpha = 255;
@ -564,9 +560,6 @@ void dss_init_overlays(struct platform_device *pdev)
case 2:
ovl->name = "vid2";
ovl->id = OMAP_DSS_VIDEO2;
ovl->supported_modes = cpu_is_omap34xx() ?
OMAP_DSS_COLOR_VID2_OMAP3 :
OMAP_DSS_COLOR_VID_OMAP2;
ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
OMAP_DSS_OVL_CAP_DISPC;
ovl->info.global_alpha = 255;
@ -579,6 +572,9 @@ void dss_init_overlays(struct platform_device *pdev)
ovl->get_overlay_info = &dss_ovl_get_overlay_info;
ovl->wait_for_go = &dss_ovl_wait_for_go;
ovl->supported_modes =
dss_feat_get_supported_color_modes(ovl->id);
omap_dss_add_overlay(ovl);
r = kobject_init_and_add(&ovl->kobj, &overlay_ktype,
@ -651,7 +647,7 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force)
}
if (mgr) {
for (i = 0; i < 3; i++) {
for (i = 0; i < dss_feat_get_num_ovls(); i++) {
struct omap_overlay *ovl;
ovl = omap_dss_get_overlay(i);
if (!ovl->manager || force) {

2
drivers/video/omap2/omapfb/Kconfig
View File

@ -3,7 +3,7 @@ menuconfig FB_OMAP2
depends on FB && OMAP2_DSS
select OMAP2_VRAM
select OMAP2_VRFB
select OMAP2_VRFB if ARCH_OMAP2 || ARCH_OMAP3
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT

26
drivers/video/omap2/omapfb/omapfb-main.c
View File

@ -714,10 +714,10 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
var->pixclock = timings.pixel_clock != 0 ?
KHZ2PICOS(timings.pixel_clock) :
0;
var->left_margin = timings.hfp;
var->right_margin = timings.hbp;
var->upper_margin = timings.vfp;
var->lower_margin = timings.vbp;
var->left_margin = timings.hbp;
var->right_margin = timings.hfp;
var->upper_margin = timings.vbp;
var->lower_margin = timings.vfp;
var->hsync_len = timings.hsw;
var->vsync_len = timings.vsw;
} else {
@ -2059,10 +2059,10 @@ static int omapfb_mode_to_timings(const char *mode_str,
if (r != 0) {
timings->pixel_clock = PICOS2KHZ(var.pixclock);
timings->hfp = var.left_margin;
timings->hbp = var.right_margin;
timings->vfp = var.upper_margin;
timings->vbp = var.lower_margin;
timings->hbp = var.left_margin;
timings->hfp = var.right_margin;
timings->vbp = var.upper_margin;
timings->vfp = var.lower_margin;
timings->hsw = var.hsync_len;
timings->vsw = var.vsync_len;
timings->x_res = var.xres;
@ -2198,6 +2198,16 @@ static int omapfb_probe(struct platform_device *pdev)
goto err0;
}
/* TODO : Replace cpu check with omap_has_vrfb once HAS_FEATURE
* available for OMAP2 and OMAP3
*/
if (def_vrfb && !cpu_is_omap24xx() && !cpu_is_omap34xx()) {
def_vrfb = 0;
dev_warn(&pdev->dev, "VRFB is not supported on this hardware, "
"ignoring the module parameter vrfb=y\n");
}
mutex_init(&fbdev->mtx);
fbdev->dev = &pdev->dev;