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[PATCH] skge: whitespace fixes

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Minor whitespace cleanups.

Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
Stephen Hemminger 2005-07-22 16:26:07 -07:00 committed by Jeff Garzik
parent 382317138b
commit 2c66851460
2 changed files with 13 additions and 13 deletions
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6
drivers/net/skge.c
View File

@ -248,7 +248,7 @@ static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
} else { } else {
u32 setting; u32 setting;
switch(ecmd->speed) { switch (ecmd->speed) {
case SPEED_1000: case SPEED_1000:
if (ecmd->duplex == DUPLEX_FULL) if (ecmd->duplex == DUPLEX_FULL)
setting = SUPPORTED_1000baseT_Full; setting = SUPPORTED_1000baseT_Full;
@ -1026,7 +1026,7 @@ static void bcom_check_link(struct skge_hw *hw, int port)
} }
/* Check Duplex mismatch */ /* Check Duplex mismatch */
switch(aux & PHY_B_AS_AN_RES_MSK) { switch (aux & PHY_B_AS_AN_RES_MSK) {
case PHY_B_RES_1000FD: case PHY_B_RES_1000FD:
skge->duplex = DUPLEX_FULL; skge->duplex = DUPLEX_FULL;
break; break;
@ -1097,7 +1097,7 @@ static void bcom_phy_init(struct skge_port *skge, int jumbo)
r |= XM_MMU_NO_PRE; r |= XM_MMU_NO_PRE;
xm_write16(hw, port, XM_MMU_CMD,r); xm_write16(hw, port, XM_MMU_CMD,r);
switch(id1) { switch (id1) {
case PHY_BCOM_ID1_C0: case PHY_BCOM_ID1_C0:
/* /*
* Workaround BCOM Errata for the C0 type. * Workaround BCOM Errata for the C0 type.

20
drivers/net/skge.h
View File

@ -1509,7 +1509,7 @@ enum {
PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
}; };
#define PHY_M_LED_PULS_DUR(x) ( ((x)<<12) & PHY_M_LEDC_PULS_MSK) #define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
enum { enum {
PULS_NO_STR = 0,/* no pulse stretching */ PULS_NO_STR = 0,/* no pulse stretching */
@ -1522,7 +1522,7 @@ enum {
PULS_1300MS = 7,/* 1.3 s to 2.7 s */ PULS_1300MS = 7,/* 1.3 s to 2.7 s */
}; };
#define PHY_M_LED_BLINK_RT(x) ( ((x)<<8) & PHY_M_LEDC_BL_R_MSK) #define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
enum { enum {
BLINK_42MS = 0,/* 42 ms */ BLINK_42MS = 0,/* 42 ms */
@ -1602,9 +1602,9 @@ enum {
PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
}; };
#define PHY_M_FELP_LED2_CTRL(x) ( ((x)<<8) & PHY_M_FELP_LED2_MSK) #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
#define PHY_M_FELP_LED1_CTRL(x) ( ((x)<<4) & PHY_M_FELP_LED1_MSK) #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
#define PHY_M_FELP_LED0_CTRL(x) ( ((x)<<0) & PHY_M_FELP_LED0_MSK) #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
enum { enum {
LED_PAR_CTRL_COLX = 0x00, LED_PAR_CTRL_COLX = 0x00,
@ -1640,7 +1640,7 @@ enum {
PHY_M_MAC_MD_COPPER = 5,/* Copper only */ PHY_M_MAC_MD_COPPER = 5,/* Copper only */
PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
}; };
#define PHY_M_MAC_MODE_SEL(x) ( ((x)<<7) & PHY_M_MAC_MD_MSK) #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
enum { enum {
@ -1650,10 +1650,10 @@ enum {
PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
}; };
#define PHY_M_LEDC_LOS_CTRL(x) ( ((x)<<12) & PHY_M_LEDC_LOS_MSK) #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
#define PHY_M_LEDC_INIT_CTRL(x) ( ((x)<<8) & PHY_M_LEDC_INIT_MSK) #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
#define PHY_M_LEDC_STA1_CTRL(x) ( ((x)<<4) & PHY_M_LEDC_STA1_MSK) #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
#define PHY_M_LEDC_STA0_CTRL(x) ( ((x)<<0) & PHY_M_LEDC_STA0_MSK) #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
/* GMAC registers */ /* GMAC registers */
/* Port Registers */ /* Port Registers */