mtd: nand: add generic helpers to check, match, maximize ECC settings
Driver are responsible for setting up ECC parameters correctly.
Those include:
- Check if ECC parameters specified (usually by DT) are valid
- Meet the chip's ECC requirement
- Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set
The logic can be generalized by factoring out common code.
This commit adds 3 helpers to the NAND framework:
nand_check_ecc_caps - Check if preset step_size and strength are valid
nand_match_ecc_req - Match the chip's requirement
nand_maximize_ecc - Maximize the ECC strength
To use the helpers above, a driver needs to provide:
- Data array of supported ECC step size and strength
- A hook that calculates ECC bytes from the combination of
step_size and strength.
By using those helpers, code duplication among drivers will be
reduced.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Masahiro Yamada
Boris Brezillon
parent
df8b97024e
commit
2c8f8afa7f
@ -4523,6 +4523,226 @@ static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
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}
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}
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/**
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* nand_check_ecc_caps - check the sanity of preset ECC settings
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* @chip: nand chip info structure
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* @caps: ECC caps info structure
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* @oobavail: OOB size that the ECC engine can use
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*
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* When ECC step size and strength are already set, check if they are supported
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* by the controller and the calculated ECC bytes fit within the chip's OOB.
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* On success, the calculated ECC bytes is set.
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*/
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int nand_check_ecc_caps(struct nand_chip *chip,
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const struct nand_ecc_caps *caps, int oobavail)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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const struct nand_ecc_step_info *stepinfo;
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int preset_step = chip->ecc.size;
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int preset_strength = chip->ecc.strength;
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int nsteps, ecc_bytes;
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int i, j;
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if (WARN_ON(oobavail < 0))
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return -EINVAL;
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if (!preset_step || !preset_strength)
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return -ENODATA;
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nsteps = mtd->writesize / preset_step;
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for (i = 0; i < caps->nstepinfos; i++) {
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stepinfo = &caps->stepinfos[i];
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if (stepinfo->stepsize != preset_step)
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continue;
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for (j = 0; j < stepinfo->nstrengths; j++) {
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if (stepinfo->strengths[j] != preset_strength)
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continue;
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ecc_bytes = caps->calc_ecc_bytes(preset_step,
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preset_strength);
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if (WARN_ON_ONCE(ecc_bytes < 0))
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return ecc_bytes;
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if (ecc_bytes * nsteps > oobavail) {
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pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
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preset_step, preset_strength);
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return -ENOSPC;
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}
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chip->ecc.bytes = ecc_bytes;
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return 0;
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}
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}
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pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
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preset_step, preset_strength);
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return -ENOTSUPP;
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}
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EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
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/**
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* nand_match_ecc_req - meet the chip's requirement with least ECC bytes
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* @chip: nand chip info structure
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* @caps: ECC engine caps info structure
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* @oobavail: OOB size that the ECC engine can use
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*
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* If a chip's ECC requirement is provided, try to meet it with the least
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* number of ECC bytes (i.e. with the largest number of OOB-free bytes).
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* On success, the chosen ECC settings are set.
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*/
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int nand_match_ecc_req(struct nand_chip *chip,
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const struct nand_ecc_caps *caps, int oobavail)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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const struct nand_ecc_step_info *stepinfo;
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int req_step = chip->ecc_step_ds;
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int req_strength = chip->ecc_strength_ds;
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int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
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int best_step, best_strength, best_ecc_bytes;
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int best_ecc_bytes_total = INT_MAX;
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int i, j;
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if (WARN_ON(oobavail < 0))
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return -EINVAL;
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/* No information provided by the NAND chip */
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if (!req_step || !req_strength)
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return -ENOTSUPP;
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/* number of correctable bits the chip requires in a page */
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req_corr = mtd->writesize / req_step * req_strength;
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for (i = 0; i < caps->nstepinfos; i++) {
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stepinfo = &caps->stepinfos[i];
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step_size = stepinfo->stepsize;
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for (j = 0; j < stepinfo->nstrengths; j++) {
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strength = stepinfo->strengths[j];
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/*
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* If both step size and strength are smaller than the
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* chip's requirement, it is not easy to compare the
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* resulted reliability.
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*/
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if (step_size < req_step && strength < req_strength)
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continue;
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if (mtd->writesize % step_size)
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continue;
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nsteps = mtd->writesize / step_size;
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ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
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if (WARN_ON_ONCE(ecc_bytes < 0))
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continue;
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ecc_bytes_total = ecc_bytes * nsteps;
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if (ecc_bytes_total > oobavail ||
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strength * nsteps < req_corr)
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continue;
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/*
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* We assume the best is to meet the chip's requrement
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* with the least number of ECC bytes.
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*/
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if (ecc_bytes_total < best_ecc_bytes_total) {
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best_ecc_bytes_total = ecc_bytes_total;
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best_step = step_size;
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best_strength = strength;
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best_ecc_bytes = ecc_bytes;
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}
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}
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}
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if (best_ecc_bytes_total == INT_MAX)
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return -ENOTSUPP;
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chip->ecc.size = best_step;
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chip->ecc.strength = best_strength;
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chip->ecc.bytes = best_ecc_bytes;
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return 0;
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}
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EXPORT_SYMBOL_GPL(nand_match_ecc_req);
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/**
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* nand_maximize_ecc - choose the max ECC strength available
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* @chip: nand chip info structure
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* @caps: ECC engine caps info structure
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* @oobavail: OOB size that the ECC engine can use
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*
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* Choose the max ECC strength that is supported on the controller, and can fit
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* within the chip's OOB. On success, the chosen ECC settings are set.
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*/
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int nand_maximize_ecc(struct nand_chip *chip,
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const struct nand_ecc_caps *caps, int oobavail)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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const struct nand_ecc_step_info *stepinfo;
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int step_size, strength, nsteps, ecc_bytes, corr;
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int best_corr = 0;
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int best_step = 0;
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int best_strength, best_ecc_bytes;
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int i, j;
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if (WARN_ON(oobavail < 0))
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return -EINVAL;
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for (i = 0; i < caps->nstepinfos; i++) {
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stepinfo = &caps->stepinfos[i];
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step_size = stepinfo->stepsize;
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/* If chip->ecc.size is already set, respect it */
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if (chip->ecc.size && step_size != chip->ecc.size)
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continue;
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for (j = 0; j < stepinfo->nstrengths; j++) {
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strength = stepinfo->strengths[j];
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if (mtd->writesize % step_size)
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continue;
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nsteps = mtd->writesize / step_size;
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ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
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if (WARN_ON_ONCE(ecc_bytes < 0))
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continue;
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if (ecc_bytes * nsteps > oobavail)
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continue;
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corr = strength * nsteps;
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/*
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* If the number of correctable bits is the same,
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* bigger step_size has more reliability.
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*/
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if (corr > best_corr ||
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(corr == best_corr && step_size > best_step)) {
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best_corr = corr;
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best_step = step_size;
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best_strength = strength;
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best_ecc_bytes = ecc_bytes;
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}
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}
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}
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if (!best_corr)
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return -ENOTSUPP;
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chip->ecc.size = best_step;
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chip->ecc.strength = best_strength;
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chip->ecc.bytes = best_ecc_bytes;
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return 0;
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}
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EXPORT_SYMBOL_GPL(nand_maximize_ecc);
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/*
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* Check if the chip configuration meet the datasheet requirements.
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@ -481,6 +481,30 @@ static inline void nand_hw_control_init(struct nand_hw_control *nfc)
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init_waitqueue_head(&nfc->wq);
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}
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/**
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* struct nand_ecc_step_info - ECC step information of ECC engine
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* @stepsize: data bytes per ECC step
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* @strengths: array of supported strengths
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* @nstrengths: number of supported strengths
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*/
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struct nand_ecc_step_info {
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int stepsize;
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const int *strengths;
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int nstrengths;
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};
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/**
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* struct nand_ecc_caps - capability of ECC engine
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* @stepinfos: array of ECC step information
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* @nstepinfos: number of ECC step information
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* @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
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*/
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struct nand_ecc_caps {
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const struct nand_ecc_step_info *stepinfos;
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int nstepinfos;
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int (*calc_ecc_bytes)(int step_size, int strength);
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};
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/**
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* struct nand_ecc_ctrl - Control structure for ECC
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* @mode: ECC mode
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@ -1246,6 +1270,15 @@ int nand_check_erased_ecc_chunk(void *data, int datalen,
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void *extraoob, int extraooblen,
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int threshold);
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int nand_check_ecc_caps(struct nand_chip *chip,
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const struct nand_ecc_caps *caps, int oobavail);
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int nand_match_ecc_req(struct nand_chip *chip,
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const struct nand_ecc_caps *caps, int oobavail);
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int nand_maximize_ecc(struct nand_chip *chip,
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const struct nand_ecc_caps *caps, int oobavail);
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/* Default write_oob implementation */
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int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
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