From 769fe42092a68dc34c1897673e781489428a108d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 7 Jul 2022 09:08:58 -0700 Subject: [PATCH 01/53] arm64: dts: qcom: sc8280xp: Add lost ranges for timer The timer node needs ranges specified to map the 1-cell children to the 2-cell address range used in /soc. This addition never made it into the patch that was posted and merged, so add it now. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Bjorn Andersson Reviewed-by: Johan Hovold Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20220707160858.3178771-1-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 7945cbb57bb4..81f1e2c6ab28 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1665,6 +1665,7 @@ reg = <0x0 0x17c20000 0x0 0x1000>; #address-cells = <1>; #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; frame@17c21000 { frame-number = <0>; From 50ed9fffec3aed88bc1ffed277d291f81153bd5d Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 7 Jul 2022 19:37:33 +0200 Subject: [PATCH 02/53] arm64: dts: qcom: ipq8074: add APCS node APCS now has support for providing the APSS clocks as the child device for IPQ8074. So, add the required DT node for it as it will later be used as the CPU clocksource. Signed-off-by: Robert Marko Reviewed-by: Dmitry Baryshkov [bjorn: Sorted node based on address] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220707173733.404947-4-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index edcb6a500175..14487a39fb6c 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -662,6 +662,14 @@ timeout-sec = <30>; }; + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq8074-apcs-apps-global"; + reg = <0x0b111000 0x6000>; + + #clock-cells = <1>; + #mbox-cells = <1>; + }; + timer@b120000 { #address-cells = <1>; #size-cells = <1>; From 1d52eb6cc827d0f166c728a7577609de75b6b8b1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 8 Jul 2022 12:16:54 +0300 Subject: [PATCH 03/53] arm64: dts: qcom: sdm845: rename DPU device node Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220708091656.2769390-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 7fb10c2ef2fb..5912ca78daa1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4329,7 +4329,7 @@ #size-cells = <2>; ranges; - mdss_mdp: mdp@ae01000 { + mdss_mdp: display-controller@ae01000 { compatible = "qcom,sdm845-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; From 37e3558b79392ab864fe887b4593c5f737e063a5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 8 Jul 2022 12:16:55 +0300 Subject: [PATCH 04/53] arm64: dts: qcom: sc7180: rename DPU device node Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220708091656.2769390-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 881e30953c0f..23aa94e66827 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2911,7 +2911,7 @@ status = "disabled"; - mdp: mdp@ae01000 { + mdp: display-controller@ae01000 { compatible = "qcom,sc7180-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; From ce5cf986cdab1973df0042ac5b743d5df008c338 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 8 Jul 2022 12:16:56 +0300 Subject: [PATCH 05/53] arm64: dts: qcom: sm8250: rename DPU device node Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220708091656.2769390-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 92fb49beda15..cc50721c1f3c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3450,7 +3450,7 @@ #size-cells = <2>; ranges; - mdss_mdp: mdp@ae01000 { + mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8250-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; From f32660459d12ad4ce54d0f0c226b3e1f34949a3a Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 8 Jul 2022 15:38:45 +0200 Subject: [PATCH 06/53] arm64: dts: qcom: ipq8074: add #size/address-cells to DTSI Add #size-cells and #address-cells to the SoC DTSI to avoid duplicating the same properties in board DTS files. Remove the mentioned properties from current board DTS files. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220708133846.599735-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 -- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 3 --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 +++ 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index de20cb98acd3..33145ec5a7d9 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -5,8 +5,6 @@ #include "ipq8074.dtsi" / { - #address-cells = <0x2>; - #size-cells = <0x2>; model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; interrupt-parent = <&intc>; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index ce86d9b10d69..c67181b173ca 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -7,9 +7,6 @@ #include "ipq8074.dtsi" / { - #address-cells = <0x2>; - #size-cells = <0x2>; - interrupt-parent = <&intc>; aliases { diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 14487a39fb6c..e516d13b8f98 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -7,6 +7,9 @@ #include / { + #address-cells = <2>; + #size-cells = <2>; + model = "Qualcomm Technologies, Inc. IPQ8074"; compatible = "qcom,ipq8074"; From b97e6ffa7c75ab30e1994997d44220fbe2799906 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 8 Jul 2022 15:38:46 +0200 Subject: [PATCH 07/53] arm64: dts: qcom: ipq8074: add interrupt-parent to DTSI Add interrupt-parent to the SoC DTSI to avoid duplicating it in each board DTS file. Remove interrupt-parent from existing board DTS files. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220708133846.599735-2-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 1 - arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 2 -- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 + 3 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index 33145ec5a7d9..81dc3a0bcd7d 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -7,7 +7,6 @@ / { model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; - interrupt-parent = <&intc>; aliases { serial0 = &blsp1_uart5; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index c67181b173ca..40415d988e4a 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -7,8 +7,6 @@ #include "ipq8074.dtsi" / { - interrupt-parent = <&intc>; - aliases { serial0 = &blsp1_uart5; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index e516d13b8f98..d53675fc1595 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -12,6 +12,7 @@ model = "Qualcomm Technologies, Inc. IPQ8074"; compatible = "qcom,ipq8074"; + interrupt-parent = <&intc>; clocks { sleep_clk: sleep_clk { From 7a9016dbc8760c4f8a610e5cb0ae0f815b0cca81 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 8 May 2022 00:46:45 +0200 Subject: [PATCH 08/53] arm64: dts: qcom: sm6350: Replace literal rpmhpd indices with constants It seems the SM6350_CX definition was temporarily replaced with its literal value 0 in 1797e1c9a95c ("arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes") to prevent a dependency on the qcom-rpmpd.h header patch being available prior to this DT patch being applied, similar to c23f1b77358c ("arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX"). However, unlike the revert of that in the sm6125 tree the next merge window around in a90b8adfa2dd ("Revert "arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX""), this has not yet happened for sm6350: replace them back now that the definitions are definitely available. Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220507224645.2238421-1-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index bb9349bc2d35..d06aefdf3d9e 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -489,7 +489,7 @@ clock-names = "iface", "core", "xo"; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040868>; - power-domains = <&rpmhpd 0>; + power-domains = <&rpmhpd SM6350_CX>; operating-points-v2 = <&sdhc1_opp_table>; bus-width = <8>; non-removable; @@ -935,7 +935,7 @@ clock-names = "iface", "core", "xo"; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; - power-domains = <&rpmhpd 0>; + power-domains = <&rpmhpd SM6350_CX>; operating-points-v2 = <&sdhc2_opp_table>; bus-width = <4>; From 2aa54fa87cca1fa43870a9caf4fcce00eb087fa5 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sat, 7 May 2022 17:36:27 +0200 Subject: [PATCH 09/53] arm64: dts: qcom: msm8998: Make regulator voltages multiple of step-size These voltages are not a multiple of the given step-size 8000 (with base voltage 1664000) in pm8998_pldo, resulting in PLDO regulators l18 and l22 failing to validate and in turn not probing the rpm-pm8998-regulator driver: l18: unsupportable voltage constraints 2856000-2848000uV qcom_rpm_smd_regulator rpm-glink:rpm-requests:pm8998-regulators: l18: devm_regulator_register() failed, ret=-22 Round the voltages down for the sake of erring on the safe side, leaving a comment in place to document this discrepancy wrt downstream sources. Fixes: 390883af89d2 ("arm64: dts: qcom: msm8998: Introduce support for Sony Yoshino platform") Reported-by: Konrad Dybcio Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220507153627.1478268-1-marijn.suijten@somainline.org --- .../dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts index 4a1f98a21031..c21333aa73c2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts @@ -26,11 +26,13 @@ }; &vreg_l18a_2p85 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; + /* Note: Round-down from 2850000 to be a multiple of PLDO step-size 8000 */ + regulator-min-microvolt = <2848000>; + regulator-max-microvolt = <2848000>; }; &vreg_l22a_2p85 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; + /* Note: Round-down from 2700000 to be a multiple of PLDO step-size 8000 */ + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2696000>; }; From 49ac5e0c3078012480749102dd3f405770a0e281 Mon Sep 17 00:00:00 2001 From: Srinivasa Rao Mandadapu Date: Thu, 7 Jul 2022 18:06:21 +0530 Subject: [PATCH 10/53] arm64: dts: qcom: sc7280: Move wcd specific pin conf to common file Move wcd specific pin conf to common file to support various herbronie variant boards and to avoid duplicate nodes in dts files. Signed-off-by: Srinivasa Rao Mandadapu Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1657197381-1271-1-git-send-email-quic_srivasam@quicinc.com --- .../qcom/sc7280-herobrine-audio-wcd9385.dtsi | 64 +++++++++++++++++++ .../boot/dts/qcom/sc7280-herobrine-crd.dts | 61 ------------------ 2 files changed, 64 insertions(+), 61 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi index 32a1e78982b2..859faaa8b7e0 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi @@ -5,6 +5,70 @@ * Copyright (c) 2022, The Linux Foundation. All rights reserved. */ +/* PINCTRL */ + +&lpass_dmic01_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic01_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic01_data { + bias-pull-down; +}; + +&lpass_dmic23_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic23_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic23_data { + bias-pull-down; +}; + +&lpass_rx_swr_clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; +}; + +&lpass_rx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_rx_swr_data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; +}; + +&lpass_rx_swr_data_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; +}; + +&lpass_tx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; +}; + &mi2s1_data0 { drive-strength = <6>; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index e9ca6c5d24a1..7881bbc641a0 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -155,67 +155,6 @@ ap_ts_pen_1v8: &i2c13 { * - If a pin is totally internal to Qcard then it gets Qcard name. * - If a pin is not hooked up on Qcard, it gets no name. */ -&lpass_dmic01_clk { - drive-strength = <8>; - bias-disable; -}; - -&lpass_dmic01_clk_sleep { - drive-strength = <2>; -}; - -&lpass_dmic01_data { - bias-pull-down; -}; - -&lpass_dmic23_clk { - drive-strength = <8>; - bias-disable; -}; - -&lpass_dmic23_clk_sleep { - drive-strength = <2>; -}; - -&lpass_dmic23_data { - bias-pull-down; -}; - -&lpass_rx_swr_clk { - drive-strength = <2>; - slew-rate = <1>; - bias-disable; -}; - -&lpass_rx_swr_clk_sleep { - bias-pull-down; -}; - -&lpass_rx_swr_data { - drive-strength = <2>; - slew-rate = <1>; - bias-bus-hold; -}; - -&lpass_rx_swr_data_sleep { - bias-pull-down; -}; - -&lpass_tx_swr_clk { - drive-strength = <2>; - slew-rate = <1>; - bias-disable; -}; - -&lpass_tx_swr_clk_sleep { - bias-pull-down; -}; - -&lpass_tx_swr_data { - drive-strength = <2>; - slew-rate = <1>; - bias-bus-hold; -}; &pm8350c_gpios { gpio-line-names = "FLASH_STROBE_1", /* 1 */ From b7b17c6bf3d18d12f198a5ab6ae2f093545de643 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 10 Jul 2022 11:41:25 +0300 Subject: [PATCH 11/53] arm64: dts: qcom: sc7180: split register block for DP controller Follow the schema for the DP controller and declare 5 register regions instead of using a single region for all the registers. Note, this extends the dts by adding p1 region to the DP node (to be used for DP MST). Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220710084133.30976-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 23aa94e66827..a81fd1130537 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3080,7 +3080,11 @@ compatible = "qcom,sc7180-dp"; status = "disabled"; - reg = <0 0x0ae90000 0 0x1400>; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0xc00>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; From ae0f7e1d97cb047ab5aeb03c8987671a2da93030 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 10 Jul 2022 11:41:26 +0300 Subject: [PATCH 12/53] arm64: dts: qcom: sc7180: drop #clock-cells from displayport-controller Drop #clock-cells from DP device node. It is a leftover from the times before splitting the device into controller and PHY devices. Now the clocks are provided by the PHY, while the controller doesn't provide any clocks. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220710084133.30976-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a81fd1130537..b82c335c25af 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3096,7 +3096,6 @@ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; From 3c14a456ee3e94d58682f6c7c77f8e71cbbcd8d8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 10 Jul 2022 11:41:27 +0300 Subject: [PATCH 13/53] arm64: dts: qcom: sc7280: split register block for DP controller Follow the schema for the DP controller and declare 5 register regions instead of using a single region for all the registers. Note, this extends the dts by adding p1 region to the DP node (to be used for DP MST). Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220710084133.30976-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ef431c954ab5..3f8b50863ba7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3810,7 +3810,11 @@ mdss_dp: displayport-controller@ae90000 { compatible = "qcom,sc7280-dp"; - reg = <0 0x0ae90000 0 0x1400>; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0xc00>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; From 0f1e23651a0ab71c82ab098ecbfc9ee7a4d74ced Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 10 Jul 2022 11:41:28 +0300 Subject: [PATCH 14/53] arm64: dts: qcom: sc7280: drop #clock-cells from displayport-controller Drop #clock-cells from DP device node. It is a leftover from the times before splitting the deviice into controller and PHY devices. Now the clocks are provided by the PHY, while the controller doesn't provide any clocks. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220710084133.30976-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3f8b50863ba7..02d5253b0167 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3730,7 +3730,6 @@ "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; @@ -3829,7 +3828,6 @@ "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; From 97e5c82d4e170b815fe31fb91d6639be0f1b11aa Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 10 Jul 2022 11:41:29 +0300 Subject: [PATCH 15/53] arm64: dts: qcom: sc7280: drop address/size-cells from eDP node Drop #address/#size-cells from eDP device node. For eDP the panels are not described directly under the controller node. They are either present under aux-bus child node, or they are declared separately (e.g. in a /soc node). Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220710084133.30976-6-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 02d5253b0167..972f8fa50959 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3740,9 +3740,6 @@ operating-points-v2 = <&edp_opp_table>; power-domains = <&rpmhpd SC7280_CX>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; ports { From f32894b8d8b4300693f1c3549cad544799ffeb3b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 10 Jul 2022 11:41:30 +0300 Subject: [PATCH 16/53] arm64: dts: qcom: sc7280: drop unused clocks from eDP node The eDP node includes two clocks which are used by the eDP PHY rather than eDP controller itself. Drop these clocks to remove extra difference between eDP and DP controllers. Suggested-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220710084133.30976-7-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 972f8fa50959..f5e8619c26b1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3716,16 +3716,12 @@ interrupt-parent = <&mdss>; interrupts = <14>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_EDP_CLKREF_EN>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; - clock-names = "core_xo", - "core_ref", - "core_iface", + clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", From 58577966a42fc0b660b5e2c7c9e5a2241363ea83 Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Mon, 11 Jul 2022 14:00:38 +0530 Subject: [PATCH 17/53] arm64: dts: qcom: qcs404: Fix incorrect USB2 PHYs assignment Currently the DT for QCS404 SoC has setup for 2 USB2 PHYs with one each assigned to USB3 controller and USB2 controller. This assignment is incorrect which only works by luck: as when each USB HCI comes up it configures the *other* controllers PHY which is enough to make them happy. If, for any reason, we were to disable one of the controllers then both would stop working. This was a difficult inconsistency to be caught which was found while trying to enable USB support in u-boot. So with all the required drivers ported to u-boot, I couldn't get the same USB storage device enumerated in u-boot which was being enumerated fine by the kernel. The root cause of the problem came out to be that I wasn't enabling USB2 PHY: "usb2_phy_prim" in u-boot. Then I realised that via simply disabling the same USB2 PHY currently assigned to USB2 host controller in the kernel disabled enumeration for USB3 host controller as well. So fix this inconsistency by correctly assigning USB2 PHYs. Fixes: 9375e7d719b3 ("arm64: dts: qcom: qcs404: Add USB devices and PHYs") Signed-off-by: Sumit Garg Reviewed-by: Daniel Thompson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220711083038.1518529-1-sumit.garg@linaro.org --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 19fd8a2b551e..9ab990061522 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -548,7 +548,7 @@ compatible = "snps,dwc3"; reg = <0x07580000 0xcd00>; interrupts = ; - phys = <&usb2_phy_sec>, <&usb3_phy>; + phys = <&usb2_phy_prim>, <&usb3_phy>; phy-names = "usb2-phy", "usb3-phy"; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; @@ -577,7 +577,7 @@ compatible = "snps,dwc3"; reg = <0x078c0000 0xcc00>; interrupts = ; - phys = <&usb2_phy_prim>; + phys = <&usb2_phy_sec>; phy-names = "usb2-phy"; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; From 1189a9cf144a745e4b98ff4f6cf5f79ab0b56cfb Mon Sep 17 00:00:00 2001 From: Parikshit Pareek Date: Mon, 11 Jul 2022 23:11:33 +0530 Subject: [PATCH 18/53] arm64: dts: qcom: sc8280xp: fix the smmu interrupt values There has been wrong values introduced for context interrupt for smu node apps_smmu. Fix those ones with due correction. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Parikshit Pareek Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220711174133.28882-1-quic_ppareek@quicinc.com --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 81f1e2c6ab28..4101c527c894 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1580,7 +1580,6 @@ , , , - , , , , @@ -1591,6 +1590,7 @@ , , , + , , , , From 39aa5646adae386719100e9e555a40e9db7bc4a2 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 13 Jul 2022 20:04:29 +0530 Subject: [PATCH 19/53] arm64: dts: qcom: sc8280xp: Fix PMU interrupt PPI interrupt should be 7 for the PMU. Cc: Johan Hovold Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Reported-by: Steve Capper Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220713143429.22624-1-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 4101c527c894..1431abc18801 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -476,7 +476,7 @@ pmu { compatible = "arm,armv8-pmuv3"; - interrupts = ; + interrupts = ; }; psci { From 1583984623cfd6dc025cf5b891f7cfaf36819213 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 15 Jul 2022 18:53:44 +0200 Subject: [PATCH 20/53] arm64: dts: qcom: sc8280xp: fix usb_1 ssphy irq Fix the usb_1 SS PHY interrupt, which was mistakingly replaced with one of the usb_2 PHY interrupts. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220715165344.28822-1-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 1431abc18801..dd6e0e845029 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1345,7 +1345,7 @@ interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; + <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; From 68af5d7c6d6dae12be6bb4fb52aabe8e1b7a2fe0 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 15 Jul 2022 09:02:45 +0200 Subject: [PATCH 21/53] arm64: dts: qcom: sc8280xp: fix USB clock order and naming Fix the USB controller clock order and naming so that they match the devicetree binding. Note that the driver currently simply enables all clocks in the order that they are specified in the devicetree. Reordering the clocks as per the binding means that the only explicit ordering constraint found in the vendor driver, that cfg_noc should be enabled before the core_clk, is now honoured. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Johan Hovold Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220715070248.19078-2-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index dd6e0e845029..c33c9aedcc05 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1276,16 +1276,16 @@ #size-cells = <2>; ranges; - clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, <&gcc GCC_SYS_NOC_USB_AXI_CLK>; - clock-names = "core", "iface", "bus_aggr", "utmi", "sleep", + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, @@ -1326,16 +1326,16 @@ #size-cells = <2>; ranges; - clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, <&gcc GCC_SYS_NOC_USB_AXI_CLK>; - clock-names = "core", "iface", "bus_aggr", "utmi", "sleep", + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, From 0bd6b33c51e916e1e6cae113a48ec3c8d897d3ac Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 15 Jul 2022 09:02:46 +0200 Subject: [PATCH 22/53] arm64: dts: qcom: sc8280xp: fix USB interrupts The two single-port SC8280XP USB controllers do not have an hs_phy_irq interrupt. Instead they have a pwr_event interrupt which is distinct from the former and not yet supported by the driver. Fix the USB node interrupt names so that they match the devicetree binding. Also fix the pwr_event interrupt of the second controller which should be 811 as noticed by Andrew Halaney. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Reviewed-by: Andrew Halaney Acked-by: Krzysztof Kozlowski Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220715070248.19078-3-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index c33c9aedcc05..12267feb2fc5 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1296,8 +1296,10 @@ <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -1342,12 +1344,14 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; From 2a8d28b8af7906259efe1c3c39de0b660f9eb35b Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 15 Jul 2022 09:02:47 +0200 Subject: [PATCH 23/53] arm64: dts: qcom: sc7280: reorder USB interrupts Only one of the USB controllers supports SuperSpeed and have an SS PHY wakeup interrupt. Reorder the interrupts so that they match the updated binding which specifically has the optional interrupt last. Acked-by: Krzysztof Kozlowski Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220715070248.19078-4-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f5e8619c26b1..13d7f267b289 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3174,10 +3174,11 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 13 IRQ_TYPE_EDGE_RISING>, - <&pdc 12 IRQ_TYPE_EDGE_RISING>; + <&pdc 12 IRQ_TYPE_EDGE_RISING>, + <&pdc 13 IRQ_TYPE_EDGE_RISING>; interrupt-names = "hs_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + "dp_hs_phy_irq", + "dm_hs_phy_irq"; power-domains = <&gcc GCC_USB30_SEC_GDSC>; @@ -3357,13 +3358,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_EDGE_BOTH>, + <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_LEVEL_HIGH>; + <&pdc 17 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", - "ss_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; From 5b7e3499e3fb7874f9de3de1e7326e029e07c93c Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 15 Jul 2022 09:02:48 +0200 Subject: [PATCH 24/53] arm64: dts: qcom: reorder USB interrupts Three SoCs did not follow the interrupt order specified by the USB controller binding. While keeping the non-SuperSpeed interrupts together seems natural, reorder the interrupts to match the binding. Acked-by: Krzysztof Kozlowski Signed-off-by: Johan Hovold [bjorn: Omitted sdx65 part from this patch] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220715070248.19078-5-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++++++++++++-------- arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++++-------- 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index cc50721c1f3c..bc773e210023 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3018,11 +3018,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -3073,11 +3075,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 12 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 65c7fe54613d..e72a04411888 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2461,11 +2461,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -2509,11 +2511,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 12 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; From 5969d3290fb5daaa40446c8610b1fbbb78ff42dd Mon Sep 17 00:00:00 2001 From: Steev Klimaszewski Date: Mon, 18 Jul 2022 17:57:14 -0500 Subject: [PATCH 25/53] arm64: dts: qcom: sc8280xp: add missing 300MHz When booting a Thinkpad x13s, we see the message [ 0.997647] cpu cpu0: failed to update OPP for freq=300000 So, lets add in 300MHz to make it happy Signed-off-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220718225714.8074-1-steev@kali.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 12267feb2fc5..49ea8b5612fc 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -36,6 +36,9 @@ compatible = "operating-points-v2"; opp-shared; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; }; From 757991c0778f5c9621955358a9fbf88999131ae1 Mon Sep 17 00:00:00 2001 From: Steev Klimaszewski Date: Mon, 18 Jul 2022 18:01:08 -0500 Subject: [PATCH 26/53] arm64: dts: sdm850: Remove unnecessary turbo-mode qcom-cpufreq-hw finds turbo-mode in the LUT hardware tables and slaps the flag on the last element, so there's no reason to add it in the dts, so remove it. Signed-off-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220718230109.8193-1-steev@kali.org --- arch/arm64/boot/dts/qcom/sdm850.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850.dtsi b/arch/arm64/boot/dts/qcom/sdm850.dtsi index b1c2cf566c7a..da9f6fbe32f6 100644 --- a/arch/arm64/boot/dts/qcom/sdm850.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm850.dtsi @@ -16,6 +16,5 @@ cpu4_opp34: opp-2956800000 { opp-hz = /bits/ 64 <2956800000>; opp-peak-kBps = <7216000 25497600>; - turbo-mode; }; }; From 8ed85d1e515ff5f302a929308c7ccc06bec68632 Mon Sep 17 00:00:00 2001 From: Kuogee Hsieh Date: Mon, 11 Jul 2022 09:23:23 -0700 Subject: [PATCH 27/53] arm64: dts: qcom: sc7280: delete vdda-1p2 and vdda-0p9 from both dp and edp Both vdda-1p2-supply and vdda-0p9-supply regulators are controlled by dp combo phy. Therefore remove them from dp controller. Signed-off-by: Kuogee Hsieh Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1657556603-15024-1-git-send-email-quic_khsieh@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 2 -- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 3 --- 2 files changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index ed8008174a33..3f8996c00b05 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -435,8 +435,6 @@ ap_i2c_tpm: &i2c14 { pinctrl-names = "default"; pinctrl-0 = <&dp_hot_plug_det>; data-lanes = <0 1>; - vdda-1p2-supply = <&vdd_a_usbssdp_0_1p2>; - vdda-0p9-supply = <&vdd_a_usbssdp_0_core>; }; &mdss_mdp { diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 4c25ffc39535..7adf31bb9827 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -311,9 +311,6 @@ /* NOTE: Not all Qcards have eDP connector stuffed */ &mdss_edp { - vdda-0p9-supply = <&vdd_a_edp_0_0p9>; - vdda-1p2-supply = <&vdd_a_edp_0_1p2>; - aux-bus { edp_panel: panel { compatible = "edp-panel"; From 0f064ae7cf703b0527de3a0608ef88548fdb5d9d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sat, 16 Jul 2022 20:44:01 -0700 Subject: [PATCH 28/53] arm64: dts: qcom: sdm845: Fill in GENI DMA references The I2C and SPI might be configured in GPI DMA mode, fill in the properties needed for this. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20220717034403.2135027-2-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 90 ++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5912ca78daa1..f0e286715d1b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1208,6 +1208,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1262,6 +1265,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1278,6 +1284,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1313,6 +1322,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1329,6 +1341,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1364,6 +1379,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1380,6 +1398,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1415,6 +1436,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1431,6 +1455,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1466,6 +1493,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1482,6 +1512,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1517,6 +1550,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1533,6 +1569,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1580,6 +1619,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1653,6 +1695,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1669,6 +1714,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1704,6 +1752,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1720,6 +1771,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1755,6 +1809,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1771,6 +1828,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1806,6 +1866,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1822,6 +1885,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1857,6 +1923,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1873,6 +1942,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1908,6 +1980,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1924,6 +1999,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1959,6 +2037,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1975,6 +2056,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -2011,6 +2095,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; }; spi15: spi@a9c000 { @@ -2026,6 +2113,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; From 79cfb1124af9b55e082d9d3efbefa4d3fc8b3cdc Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sat, 16 Jul 2022 20:44:02 -0700 Subject: [PATCH 29/53] arm64: dts: qcom: sdm845-db845c: Enable gpi_dma1 Enable gpi_dma1 so that i2c14 is able to find its DMA controller. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20220717034403.2135027-3-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 4afdb72cc556..62ad67370d2b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -443,6 +443,10 @@ status = "okay"; }; +&gpi_dma1 { + status = "okay"; +}; + &gpu { status = "okay"; zap-shader { From 746ff2bfcec78cfd522b2a490e7207c3fe836634 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sat, 16 Jul 2022 20:44:03 -0700 Subject: [PATCH 30/53] arm64: dts: qcom: sdm845-db845c: Specify a i2c bus clocks The kernel log contains complaints about i2c11 and i2c14 lacking clock-frequency, specify a reasonable value to suppress this warning. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20220717034403.2135027-4-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 62ad67370d2b..c6e2c571b452 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -499,12 +499,14 @@ &i2c11 { /* On Low speed expansion */ + clock-frequency = <100000>; label = "LS-I2C1"; status = "okay"; }; &i2c14 { /* On Low speed expansion */ + clock-frequency = <100000>; label = "LS-I2C0"; status = "okay"; }; From 1282fa32d71633bce5330a592db6e53cf73d2c28 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Wed, 20 Jul 2022 02:20:57 +0530 Subject: [PATCH 31/53] arm64: dts: qcom: qrb5165-rb5: Fix 'dtbs_check' error for lpg nodes make dtbs_check currently reports the following warnings with qrb5165-rb5 lpg nodes: arch/arm64/boot/dts/qcom/qrb5165-rb5.dts: Warning (reg_format): /soc@0/spmi@c440000/pmic@5/lpg/led@1:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) arch/arm64/boot/dts/qcom/qrb5165-rb5.dts: Warning (avoid_default_addr_size): /soc@0/spmi@c440000/pmic@5/lpg/led@1: Relying on default #address-cells value Fix the same. Cc: Bjorn Andersson Cc: Dmitry Baryshkov Signed-off-by: Bhupesh Sharma Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220719205058.1004942-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index b3740375dd4c..a7278928efc1 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -816,6 +816,9 @@ &pm8150l_lpg { status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + led@1 { reg = <1>; color = ; From 360d9526761270f2497893946bb48de468a229cc Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Wed, 20 Jul 2022 02:20:58 +0530 Subject: [PATCH 32/53] arm64: dts: qcom: qrb5165-rb5: Fix 'dtbs_check' error for led nodes make dtbs_check currently reports the following errors with qrb5165-rb5 led nodes: arch/arm64/boot/dts/qcom/qrb5165-rb5.dtb: leds: 'bt', 'user4', 'wlan' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Fix the same. Also while at it, fix a blank line issue in the led node. Cc: Bjorn Andersson Cc: Dmitry Baryshkov Signed-off-by: Bhupesh Sharma Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220719205058.1004942-3-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index a7278928efc1..bf8077a1cf9a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -58,7 +58,7 @@ leds { compatible = "gpio-leds"; - user4 { + led-user4 { label = "green:user4"; function = LED_FUNCTION_INDICATOR; color = ; @@ -67,7 +67,7 @@ default-state = "off"; }; - wlan { + led-wlan { label = "yellow:wlan"; function = LED_FUNCTION_WLAN; color = ; @@ -76,7 +76,7 @@ default-state = "off"; }; - bt { + led-bt { label = "blue:bt"; function = LED_FUNCTION_BLUETOOTH; color = ; @@ -84,7 +84,6 @@ linux,default-trigger = "bluetooth-power"; default-state = "off"; }; - }; lt9611_1v2: lt9611-vdd12-regulator { From 944de5182f0269e72ffe0a8880c8dbeb30f473d8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 20 May 2022 14:32:44 +0200 Subject: [PATCH 33/53] dt-bindings: arm: qcom: fix Alcatel OneTouch Idol 3 compatibles The MSM8916 Alcatel OneTouch Idol 3 does not use MTP fallbacks in compatibles: msm8916-alcatel-idol347.dtb: /: compatible: 'oneOf' conditional failed, one must be fixed: ['alcatel,idol347', 'qcom,msm8916'] is too short Reported-by: Rob Herring Fixes: e9dd2f7204ed ("dt-bindings: arm: qcom: Document alcatel,idol347 board") Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Stephan Gerhold Link: https://lore.kernel.org/r/20220520123252.365762-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index fffd596e8901..2ecd0b9be6b1 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -159,14 +159,13 @@ properties: - const: qcom,msm8974 - items: - - enum: - - alcatel,idol347 - const: qcom,msm8916-mtp/1 - const: qcom,msm8916-mtp - const: qcom,msm8916 - items: - enum: + - alcatel,idol347 - longcheer,l8150 - samsung,a3u-eur - samsung,a5u-eur From 25d203d0751ca191301bc578ba5d59fa401f1fbf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 20 May 2022 14:32:45 +0200 Subject: [PATCH 34/53] dt-bindings: arm: qcom: fix Longcheer L8150 compatibles The MSM8916 Longcheer L8150 uses a fallback in compatible: msm8916-longcheer-l8150.dtb: /: compatible: 'oneOf' conditional failed, one must be fixed: ['longcheer,l8150', 'qcom,msm8916-v1-qrd/9-v1', 'qcom,msm8916'] is too long Fixes: b72160fa886d ("dt-bindings: qcom: Document bindings for new MSM8916 devices") Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Stephan Gerhold Link: https://lore.kernel.org/r/20220520123252.365762-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2ecd0b9be6b1..343099ee71be 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -166,11 +166,15 @@ properties: - items: - enum: - alcatel,idol347 - - longcheer,l8150 - samsung,a3u-eur - samsung,a5u-eur - const: qcom,msm8916 + - items: + - const: longcheer,l8150 + - const: qcom,msm8916-v1-qrd/9-v1 + - const: qcom,msm8916 + - items: - enum: - sony,karin_windy From bb35fe1efbae4114bd288fae0f56070f563adcfc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 20 May 2022 14:32:46 +0200 Subject: [PATCH 35/53] dt-bindings: arm: qcom: fix MSM8916 MTP compatibles The order of compatibles for MSM8916 MTP board is different: msm8916-mtp.dtb: /: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,msm8916-mtp', 'qcom,msm8916-mtp/1', 'qcom,msm8916'] is too long Fixes: 9d3ef77fe568 ("dt-bindings: arm: Convert QCom board/soc bindings to json-schema") Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220520123252.365762-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 343099ee71be..0ed1b21ed755 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -159,8 +159,8 @@ properties: - const: qcom,msm8974 - items: - - const: qcom,msm8916-mtp/1 - const: qcom,msm8916-mtp + - const: qcom,msm8916-mtp/1 - const: qcom,msm8916 - items: From c704bd373f58a84193eebe40bd271d6b73c138b0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 20 May 2022 14:32:47 +0200 Subject: [PATCH 36/53] dt-bindings: arm: qcom: fix MSM8994 boards compatibles The compatibles for APQ8094/MSM8994 boards are different than specified in bindings. None of them use fallback to other SoC variant. Fixes: 9ad3c08f6f1b ("dt-bindings: arm: qcom: Document sony boards for apq8094") Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220520123252.365762-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 0ed1b21ed755..a0a9446e6045 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -178,12 +178,15 @@ properties: - items: - enum: - sony,karin_windy + - const: qcom,apq8094 + + - items: + - enum: - sony,karin-row - sony,satsuki-row - sony,sumire-row - sony,suzuran-row - - qcom,msm8994 - - const: qcom,apq8094 + - const: qcom,msm8994 - items: - enum: From fc4f8f6748e39a05a392f5cf60d772c00bcff913 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 20 May 2022 14:32:48 +0200 Subject: [PATCH 37/53] dt-bindings: arm: qcom: add missing MSM8916 board compatibles Document several board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Stephan Gerhold Link: https://lore.kernel.org/r/20220520123252.365762-5-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index a0a9446e6045..7bf04181399a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -166,8 +166,14 @@ properties: - items: - enum: - alcatel,idol347 + - asus,z00l + - huawei,g7 + - longcheer,l8910 - samsung,a3u-eur - samsung,a5u-eur + - samsung,j5 + - samsung,serranove + - wingtech,wt88047 - const: qcom,msm8916 - items: From 940780880200c5b1dc48b0bd4f455c4fa50749af Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 20 May 2022 14:32:49 +0200 Subject: [PATCH 38/53] dt-bindings: arm: qcom: add missing MSM8994 board compatibles Document several board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220520123252.365762-6-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 7bf04181399a..1e56f986c5bf 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -188,6 +188,9 @@ properties: - items: - enum: + - huawei,angler + - microsoft,cityman + - sony,ivy-row - sony,karin-row - sony,satsuki-row - sony,sumire-row From 1ce0ff93d711f756bf906e110c45adf16f078ffe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 20 May 2022 14:32:50 +0200 Subject: [PATCH 39/53] dt-bindings: arm: qcom: add missing SM8150 board compatibles Document several board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220520123252.365762-7-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1e56f986c5bf..41cc5d8f4bfd 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -613,7 +613,11 @@ properties: - items: - enum: + - microsoft,surface-duo + - qcom,sm8150-hdk - qcom,sm8150-mtp + - sony,bahamut-generic + - sony,griffin-generic - const: qcom,sm8150 - items: From c810f39aea90e29831585f190290bfd0ba63469f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 20 May 2022 14:32:51 +0200 Subject: [PATCH 40/53] dt-bindings: arm: qcom: add missing SM8250 board compatibles Document several board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220520123252.365762-8-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 41cc5d8f4bfd..539e381c7396 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -623,7 +623,10 @@ properties: - items: - enum: - qcom,qrb5165-rb5 + - qcom,sm8250-hdk - qcom,sm8250-mtp + - sony,pdx203-generic + - sony,pdx206-generic - const: qcom,sm8250 - items: From baa36665348b9f8df2a4670afcbec86d3260a75e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 20 May 2022 14:32:52 +0200 Subject: [PATCH 41/53] dt-bindings: arm: qcom: add missing SM8350 board compatibles Document several board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220520123252.365762-9-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 539e381c7396..cf6d31c30111 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -631,8 +631,11 @@ properties: - items: - enum: + - microsoft,surface-duo2 - qcom,sm8350-hdk - qcom,sm8350-mtp + - sony,pdx214-generic + - sony,pdx215-generic - const: qcom,sm8350 - items: From 82a547bb3ceeb2b948da161a7ac8cf45987d36ec Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 21 May 2022 18:45:39 +0200 Subject: [PATCH 42/53] dt-bindings: vendor-prefixes: add Shift GmbH Add prefix for SHIFT GmbH, phone manufacturer (https://www.shiftphones.com/en/). Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220521164550.91115-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6bb20b4554d7..d5b49e4773b8 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1098,6 +1098,8 @@ patternProperties: description: SGX Sensortech "^sharp,.*": description: Sharp Corporation + "^shift,.*": + description: SHIFT GmbH "^shimafuji,.*": description: Shimafuji Electric, Inc. "^shiratech,.*": From 8eb1b188caf70f3d15ed924a53dc0d74818524e8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 21 May 2022 18:45:40 +0200 Subject: [PATCH 43/53] dt-bindings: arm: qcom: add missing MSM8998 board compatibles Document board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220521164550.91115-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index cf6d31c30111..81dacfc26d82 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -38,6 +38,7 @@ description: | msm8992 msm8994 msm8996 + msm8998 sa8155p sa8540p sc7180 @@ -215,6 +216,20 @@ properties: - xiaomi,scorpio - const: qcom,msm8996 + - items: + - enum: + - asus,novago-tp370ql + - fxtec,pro1 + - hp,envy-x2 + - lenovo,miix-630 + - oneplus,cheeseburger + - oneplus,dumpling + - qcom,msm8998-mtp + - sony,xperia-lilac + - sony,xperia-maple + - sony,xperia-poplar + - const: qcom,msm8998 + - items: - enum: - qcom,ipq4019-ap-dk01.1-c1 From 02cb8d73c0d663cd7b38668963a92c743814d391 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 21 May 2022 18:45:41 +0200 Subject: [PATCH 44/53] dt-bindings: arm: qcom: add missing MSM8992 board compatibles Document board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220521164550.91115-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 81dacfc26d82..e6e58233cba8 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -182,6 +182,13 @@ properties: - const: qcom,msm8916-v1-qrd/9-v1 - const: qcom,msm8916 + - items: + - enum: + - lg,bullhead + - microsoft,talkman + - xiaomi,libra + - const: qcom,msm8992 + - items: - enum: - sony,karin_windy From 09b75a927ffd453a4bc25d88d4c4dca3b12eaf99 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 21 May 2022 18:45:42 +0200 Subject: [PATCH 45/53] dt-bindings: arm: qcom: add missing QCS404 board compatibles Document board compatibles already present in Linux kernel. In itself this resulted in a dt_binding_check in qcom-cpufrq-nvmem.yaml, which was reported by Rob, solved in below change by Krzysztof and acked by Viresh. The fix is squashed into this to avoid bisect problems. Link: https://lore.kernel.org/r/20220627143340.477120-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220521164550.91115-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++ .../devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index e6e58233cba8..7f158fd31263 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -39,6 +39,7 @@ description: | msm8994 msm8996 msm8998 + qcs404 sa8155p sa8540p sc7180 @@ -618,6 +619,13 @@ properties: - qcom,ipq6018-cp01-c1 - const: qcom,ipq6018 + - items: + - enum: + - qcom,qcs404-evb-1000 + - qcom,qcs404-evb-4000 + - const: qcom,qcs404-evb + - const: qcom,qcs404 + - items: - enum: - qcom,sa8155p-adp diff --git a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml index a9a776da5505..10b3a7a4af36 100644 --- a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml +++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml @@ -63,8 +63,8 @@ additionalProperties: true examples: - | / { - model = "Qualcomm Technologies, Inc. QCS404"; - compatible = "qcom,qcs404"; + model = "Qualcomm Technologies, Inc. QCS404 EVB 1000"; + compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404"; #address-cells = <2>; #size-cells = <2>; From 0d45153fb9bb221480c27f637e56886bb387cb58 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 21 May 2022 18:45:43 +0200 Subject: [PATCH 46/53] dt-bindings: arm: qcom: add missing SDM630 board compatibles Document board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220521164550.91115-5-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 7f158fd31263..846daeac212b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -586,6 +586,14 @@ properties: - qcom,sc8280xp-qrd - const: qcom,sc8280xp + - items: + - enum: + - sony,discovery-row + - sony,kirin-row + - sony,pioneer-row + - sony,voyager-row + - const: qcom,sdm630 + - items: - enum: - inforce,ifc6560 From ce23114d25dc68e3100057af31f6c4bfde138430 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 21 May 2022 18:45:44 +0200 Subject: [PATCH 47/53] dt-bindings: arm: qcom: add missing SDM636 board compatibles Document board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220521164550.91115-6-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 846daeac212b..eac9d6d5a231 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -49,6 +49,7 @@ description: | sda660 sdm630 sdm632 + sdm636 sdm660 sdm845 sdx55 @@ -604,6 +605,11 @@ properties: - fairphone,fp3 - const: qcom,sdm632 + - items: + - enum: + - sony,mermaid-row + - const: qcom,sdm636 + - items: - enum: - xiaomi,lavender From 33fae534d7b1420ea958955834cfa464c58e4305 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 21 May 2022 18:45:45 +0200 Subject: [PATCH 48/53] dt-bindings: arm: qcom: add missing SDM845 board compatibles Document board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220521164550.91115-7-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index eac9d6d5a231..f18e7989d451 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -650,6 +650,21 @@ properties: - qcom,sa8295p-adp - const: qcom,sa8540p + - items: + - enum: + - lenovo,yoga-c630 + - oneplus,enchilada + - oneplus,fajita + - qcom,sdm845-mtp + - shift,axolotl + - samsung,w737 + - sony,akari-row + - sony,akatsuki-row + - sony,apollo-row + - thundercomm,db845c + - xiaomi,beryllium + - const: qcom,sdm845 + - items: - enum: - fairphone,fp4 From d3ddba6a25dc16f2679717cec773118fc8baf5fa Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 21 May 2022 18:45:46 +0200 Subject: [PATCH 49/53] dt-bindings: arm: qcom: add missing SM6125 board compatibles Document board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220521164550.91115-8-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f18e7989d451..66b0e5b71c38 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -54,6 +54,7 @@ description: | sdm845 sdx55 sdx65 + sm6125 sm7225 sm8150 sm8250 @@ -665,6 +666,11 @@ properties: - xiaomi,beryllium - const: qcom,sdm845 + - items: + - enum: + - sony,pdx201 + - const: qcom,sm6125 + - items: - enum: - fairphone,fp4 From 31b3483aaa180b88f90861d5113c342442f3646f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 21 May 2022 18:45:47 +0200 Subject: [PATCH 50/53] dt-bindings: arm: qcom: add missing SM6350 board compatibles Document board compatibles already present in Linux kernel. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220521164550.91115-9-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 66b0e5b71c38..60f37ee50797 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -55,6 +55,7 @@ description: | sdx55 sdx65 sm6125 + sm6350 sm7225 sm8150 sm8250 @@ -671,6 +672,11 @@ properties: - sony,pdx201 - const: qcom,sm6125 + - items: + - enum: + - sony,pdx213 + - const: qcom,sm6350 + - items: - enum: - fairphone,fp4 From 1ef5a4d1d03cfcdb6ea24bece9e9c63ce97764fe Mon Sep 17 00:00:00 2001 From: Stefan Hansson Date: Sun, 26 Jun 2022 12:45:36 -0400 Subject: [PATCH 51/53] dt-bindings: arm: qcom: Document lg,judyln and lg,judyp devices Add binding documentation for the LG G7 and LG V35 smartphones which are based on Snapdragon 845 (sdm845). Signed-off-by: Stefan Hansson Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220626164536.16011-1-newbie13xd@gmail.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 60f37ee50797..720c421fb811 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -655,6 +655,8 @@ properties: - items: - enum: - lenovo,yoga-c630 + - lg,judyln + - lg,judyp - oneplus,enchilada - oneplus,fajita - qcom,sdm845-mtp From 5aca0822aabf4fc9c33131f0d419289fefdc70ac Mon Sep 17 00:00:00 2001 From: Molly Sophia Date: Tue, 12 Jul 2022 22:51:38 +0800 Subject: [PATCH 52/53] dt-bindings: arm: qcom: Add Xiaomi Mi Mix2s bindings Add documentation for "xiaomi,polaris" device. Signed-off-by: Molly Sophia Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220712145139.9473-1-mollysophia379@gmail.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 720c421fb811..d4873cefa660 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -667,6 +667,7 @@ properties: - sony,apollo-row - thundercomm,db845c - xiaomi,beryllium + - xiaomi,polaris - const: qcom,sdm845 - items: From be497abe19bf08fba549dd236624e7bb90597323 Mon Sep 17 00:00:00 2001 From: Molly Sophia Date: Tue, 12 Jul 2022 22:51:40 +0800 Subject: [PATCH 53/53] arm64: dts: qcom: Add support for Xiaomi Mi Mix2s Add support for Xiaomi Mi Mix2s (polaris) handsets. Currently working features: - UFS - Touchscreen - USB 2 - Bluetooth - Wi-Fi - GPU - Venus - Display (need jdi-fhd-nt35596s panel driver, which I have sent a patch but it haven't been into upstream yet) Signed-off-by: Molly Sophia Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220712145139.9473-2-mollysophia379@gmail.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sdm845-xiaomi-polaris.dts | 762 ++++++++++++++++++ 2 files changed, 763 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 9e2a13d75f9d..1d86a33de528 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts new file mode 100644 index 000000000000..7747081b9887 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -0,0 +1,762 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Xilin Wu + * Copyright (c) 2022, Molly Sophia + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" +#include "pm8005.dtsi" + +/* + * Delete following upstream (sdm845.dtsi) reserved + * memory mappings which are different in this device. + */ +/delete-node/ &rmtfs_mem; +/delete-node/ &adsp_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; + +/ { + model = "Xiaomi Mi MIX 2S"; + compatible = "xiaomi,polaris", "qcom,sdm845"; + chassis-type = "handset"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <0x141 0x20001>; + qcom,board-id = <0x2a 0x0>; + + aliases { + serial0 = &uart9; + serial1 = &uart6; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&volume_up_gpio>; + + key-vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + reserved-memory { + adsp_mem: memory@8c500000 { + reg = <0 0x8c500000 0 0x1e00000>; + no-map; + }; + + wlan_msa_mem: memory@8e300000 { + reg = <0 0x8e300000 0 0x100000>; + no-map; + }; + + mpss_region: memory@8e400000 { + reg = <0 0x8e400000 0 0x7800000>; + no-map; + }; + + venus_mem: memory@95c00000 { + reg = <0 0x95c00000 0 0x500000>; + no-map; + }; + + cdsp_mem: memory@96100000 { + reg = <0 0x96100000 0 0x800000>; + no-map; + }; + + mba_region: memory@96900000 { + reg = <0 0x96900000 0 0x200000>; + no-map; + }; + + slpi_mem: memory@96b00000 { + reg = <0 0x96b00000 0 0x1400000>; + no-map; + }; + + spss_mem: memory@97f00000 { + reg = <0 0x97f00000 0 0x100000>; + no-map; + }; + + rmtfs_mem: memory@f6301000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf6301000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + }; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <3400000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; + + vreg_tp_vddio: vreg-tp-vddio { + compatible = "regulator-fixed"; + regulator-name = "vreg_tp_vddio"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 23 0>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + vreg_s4a_1p8: vreg-s4a-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s2a_1p1: smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdda_mipi_dsi0_pll: + vdda_ufs1_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8a_1p2: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l10a_2p95: ldo10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l11a_1p05: ldo11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l18a_2p9: ldo18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l19a_3p1: ldo19 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l22a_3p3: ldo22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vdda_mipi_dsi0_1p2: + vdda_ufs1_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_smp3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-always-on; + }; + }; +}; + +&cdsp_pas { + firmware-name = "qcom/sdm845/polaris/cdsp.mbn"; + status = "okay"; +}; + +&dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + status = "okay"; + + display_panel: panel@0 { + compatible = "jdi,fhd-nt35596s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + vddio-supply = <&vreg_l14a_1p8>; + backlight = <&pmi8998_wled>; + vddpos-supply = <&lab>; + vddneg-supply = <&ibb>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active>; + pinctrl-1 = <&sde_dsi_suspend>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + status = "okay"; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&gmu { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm845/polaris/a630_zap.mbn"; + }; +}; + +&ibb { + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + regulator-over-current-protection; + regulator-pull-down; + regulator-soft-start; + qcom,discharge-resistor-kohms = <300>; +}; + +&ipa { + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm845/polaris/ipa_fws.mbn"; + status = "okay"; +}; + +&i2c14 { + clock-frequency = <400000>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts-extended = <&tlmm 125 0x2008>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ts_int_default &ts_reset_default>; + pinctrl-1 = <&ts_int_sleep &ts_reset_sleep>; + + vdd-supply = <&vreg_l28a_3p0>; + vio-supply = <&vreg_tp_vddio>; + + syna,startup-delay-ms = <0xc8>; + syna,reset-delay-ms = <0xc8>; + + rmi4-f01@1 { + syna,nosleep-mode = <0x1>; + reg = <0x1>; + }; + + rmi4-f12@12 { + syna,rezero-wait-ms = <0xc8>; + syna,clip-x-high = <0x438>; + syna,clip-y-high = <0x870>; + syna,sensor-type = <0x1>; + syna,clip-x-low = <0x0>; + syna,clip-y-low = <0x0>; + }; + }; +}; + +&lab { + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + regulator-soft-start; + regulator-pull-down; +}; + +&mdss { + status = "okay"; +}; + +&mss_pil { + firmware-name = "qcom/sdm845/polaris/mba.mbn", "qcom/sdm845/polaris/modem.mbn"; + status = "okay"; +}; + +&pmi8998_wled { + qcom,current-limit-microamp = <20000>; + qcom,current-boost-limit = <970>; + qcom,ovp-millivolt = <19600>; + qcom,switching-freq = <600>; + qcom,num-strings = <4>; + qcom,cabc; + + status = "okay"; +}; + +&pm8998_gpio { + volume_up_gpio: pm8998_gpio6 { + pinconf { + qcom,drive-strength = ; + function = "normal"; + pins = "gpio6"; + input-enable; + bias-pull-up; + }; + }; +}; + +&pm8998_pon { + resin { + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + compatible = "qcom,pm8941-resin"; + linux,code = ; + debounce = <15625>; + bias-pull-up; + }; +}; + +&q6afedai { + qi2s@22 { + reg = <22>; + qcom,sd-lines = <0>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qup_i2c14_default { + pinconf { + pins = "gpio33", "gpio34"; + drive-strength = <2>; + bias-disable; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + ts_reset_default: ts-reset-default { + pins = "gpio99"; + function = "gpio"; + drive-strength = <16>; + output-high; + }; + + ts_int_default: ts-int-default { + pins = "gpio125"; + function = "gpio"; + bias-pull-down; + drive-strength = <16>; + input-enable; + }; + + ts_reset_sleep: ts-reset-sleep { + pins = "gpio99"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + ts_int_sleep: ts-int-sleep { + pins = "gpio125"; + function = "gpio"; + bias-pull-down; + drive-strength = <2>; + input-enable; + }; + + sde_dsi_active: sde-dsi-active { + pins = "gpio6", "gpio10"; + function = "gpio"; + drive-strength = <8>; + bias-disable = <0>; + }; + + sde_dsi_suspend: sde-dsi-suspend { + pins = "gpio6", "gpio10"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wcd_intr_default: wcd-intr-default { + pins = "goui54"; + function = "gpio"; + input-enable; + bias-pull-down; + drive-strength = <2>; + }; +}; + +&uart6 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + /* This path is relative to the qca/ subdir under lib/firmware. */ + firmware-name = "polaris/crnv21.bin"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&usb_1 { + /* We'll use this as USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + + /* Fastest mode for USB 2 */ + maximum-speed = "high-speed"; + + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdd-supply = <&vreg_l1a_0p875>; + + qcom,preemphasis-width = ; + qcom,preemphasis-level = ; + qcom,hstx-trim-value = ; + qcom,imp-res-offset-value = <8>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l26a_1p2>; + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <800000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sdm845/polaris/venus.mbn"; + status = "okay"; +}; + +&wcd9340 { + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + clock-names = "extclk"; + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + reset-gpios = <&tlmm 64 0>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + + qcom,micbias1-microvolt = <2700000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <2700000>; + qcom,micbias4-microvolt = <2700000>; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + qcom,snoc-host-cap-skip-quirk; + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ + +&qup_uart6_default { + pinmux { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; + }; + + cts { + pins = "gpio45"; + bias-disable; + }; + + rts-tx { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio48"; + bias-pull-up; + }; +};