soc: mediatek: devapc: Separate register offsets from mtk_devapc_data
The register offsets is the same between MT6779 and MT8186. To reuse the register offsets, we move these register offsets to another structure "mtk_devapc_regs_ofs". Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220504115501.3490-3-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -31,10 +31,7 @@ struct mtk_devapc_vio_dbgs {
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u32 vio_dbg1;
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};
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struct mtk_devapc_data {
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/* numbers of violation index */
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u32 vio_idx_num;
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struct mtk_devapc_regs_ofs {
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/* reg offset */
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u32 vio_mask_offset;
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u32 vio_sta_offset;
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@ -46,6 +43,12 @@ struct mtk_devapc_data {
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u32 vio_shift_con_offset;
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};
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struct mtk_devapc_data {
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/* numbers of violation index */
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u32 vio_idx_num;
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const struct mtk_devapc_regs_ofs *regs_ofs;
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};
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struct mtk_devapc_context {
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struct device *dev;
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void __iomem *infra_base;
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@ -58,7 +61,7 @@ static void clear_vio_status(struct mtk_devapc_context *ctx)
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void __iomem *reg;
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int i;
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reg = ctx->infra_base + ctx->data->vio_sta_offset;
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reg = ctx->infra_base + ctx->data->regs_ofs->vio_sta_offset;
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for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
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writel(GENMASK(31, 0), reg + 4 * i);
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@ -73,7 +76,7 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask)
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u32 val;
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int i;
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reg = ctx->infra_base + ctx->data->vio_mask_offset;
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reg = ctx->infra_base + ctx->data->regs_ofs->vio_mask_offset;
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if (mask)
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val = GENMASK(31, 0);
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@ -116,11 +119,11 @@ static int devapc_sync_vio_dbg(struct mtk_devapc_context *ctx)
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u32 val;
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pd_vio_shift_sta_reg = ctx->infra_base +
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ctx->data->vio_shift_sta_offset;
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ctx->data->regs_ofs->vio_shift_sta_offset;
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pd_vio_shift_sel_reg = ctx->infra_base +
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ctx->data->vio_shift_sel_offset;
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ctx->data->regs_ofs->vio_shift_sel_offset;
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pd_vio_shift_con_reg = ctx->infra_base +
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ctx->data->vio_shift_con_offset;
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ctx->data->regs_ofs->vio_shift_con_offset;
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/* Find the minimum shift group which has violation */
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val = readl(pd_vio_shift_sta_reg);
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@ -161,8 +164,8 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
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void __iomem *vio_dbg0_reg;
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void __iomem *vio_dbg1_reg;
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vio_dbg0_reg = ctx->infra_base + ctx->data->vio_dbg0_offset;
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vio_dbg1_reg = ctx->infra_base + ctx->data->vio_dbg1_offset;
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vio_dbg0_reg = ctx->infra_base + ctx->data->regs_ofs->vio_dbg0_offset;
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vio_dbg1_reg = ctx->infra_base + ctx->data->regs_ofs->vio_dbg1_offset;
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vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
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vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
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@ -200,7 +203,7 @@ static irqreturn_t devapc_violation_irq(int irq_number, void *data)
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*/
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static void start_devapc(struct mtk_devapc_context *ctx)
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{
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writel(BIT(31), ctx->infra_base + ctx->data->apc_con_offset);
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writel(BIT(31), ctx->infra_base + ctx->data->regs_ofs->apc_con_offset);
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mask_module_irq(ctx, false);
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}
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@ -212,11 +215,10 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
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{
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mask_module_irq(ctx, true);
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writel(BIT(2), ctx->infra_base + ctx->data->apc_con_offset);
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writel(BIT(2), ctx->infra_base + ctx->data->regs_ofs->apc_con_offset);
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}
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static const struct mtk_devapc_data devapc_mt6779 = {
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.vio_idx_num = 511,
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static const struct mtk_devapc_regs_ofs devapc_regs_ofs_mt6779 = {
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.vio_mask_offset = 0x0,
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.vio_sta_offset = 0x400,
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.vio_dbg0_offset = 0x900,
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@ -227,6 +229,11 @@ static const struct mtk_devapc_data devapc_mt6779 = {
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.vio_shift_con_offset = 0xF20,
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};
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static const struct mtk_devapc_data devapc_mt6779 = {
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.vio_idx_num = 511,
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.regs_ofs = &devapc_regs_ofs_mt6779,
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};
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static const struct of_device_id mtk_devapc_dt_match[] = {
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{
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.compatible = "mediatek,mt6779-devapc",
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