soc: imx: imx8mp-blk-ctrl: expose high performance PLL clock
Expose the high performance PLL as a regular Linux clock, so the PCIe PHY can use it when there is no external refclock provided. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Lukas F. Hartmann <lukas@mntre.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -32,6 +32,7 @@ config IMX8M_BLK_CTRL
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bool
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default SOC_IMX8M && IMX_GPCV2_PM_DOMAINS
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depends on PM_GENERIC_DOMAINS
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depends on COMMON_CLK
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config IMX9_BLK_CTRL
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bool
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@ -4,7 +4,9 @@
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* Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/interconnect.h>
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#include <linux/module.h>
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@ -21,6 +23,15 @@
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#define USB_CLOCK_MODULE_EN BIT(1)
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#define PCIE_PHY_APB_RST BIT(4)
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#define PCIE_PHY_INIT_RST BIT(5)
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#define GPR_REG1 0x4
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#define PLL_LOCK BIT(13)
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#define GPR_REG2 0x8
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#define P_PLL_MASK GENMASK(5, 0)
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#define M_PLL_MASK GENMASK(15, 6)
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#define S_PLL_MASK GENMASK(18, 16)
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#define GPR_REG3 0xc
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#define PLL_CKE BIT(17)
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#define PLL_RST BIT(31)
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struct imx8mp_blk_ctrl_domain;
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@ -74,6 +85,92 @@ to_imx8mp_blk_ctrl_domain(struct generic_pm_domain *genpd)
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return container_of(genpd, struct imx8mp_blk_ctrl_domain, genpd);
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}
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struct clk_hsio_pll {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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static inline struct clk_hsio_pll *to_clk_hsio_pll(struct clk_hw *hw)
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{
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return container_of(hw, struct clk_hsio_pll, hw);
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}
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static int clk_hsio_pll_prepare(struct clk_hw *hw)
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{
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struct clk_hsio_pll *clk = to_clk_hsio_pll(hw);
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u32 val;
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/* set the PLL configuration */
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regmap_update_bits(clk->regmap, GPR_REG2,
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P_PLL_MASK | M_PLL_MASK | S_PLL_MASK,
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FIELD_PREP(P_PLL_MASK, 12) |
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FIELD_PREP(M_PLL_MASK, 800) |
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FIELD_PREP(S_PLL_MASK, 4));
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/* de-assert PLL reset */
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regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST, PLL_RST);
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/* enable PLL */
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regmap_update_bits(clk->regmap, GPR_REG3, PLL_CKE, PLL_CKE);
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return regmap_read_poll_timeout(clk->regmap, GPR_REG1, val,
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val & PLL_LOCK, 10, 100);
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}
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static void clk_hsio_pll_unprepare(struct clk_hw *hw)
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{
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struct clk_hsio_pll *clk = to_clk_hsio_pll(hw);
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regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST | PLL_CKE, 0);
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}
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static int clk_hsio_pll_is_prepared(struct clk_hw *hw)
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{
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struct clk_hsio_pll *clk = to_clk_hsio_pll(hw);
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return regmap_test_bits(clk->regmap, GPR_REG1, PLL_LOCK);
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}
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static unsigned long clk_hsio_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return 100000000;
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}
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static const struct clk_ops clk_hsio_pll_ops = {
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.prepare = clk_hsio_pll_prepare,
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.unprepare = clk_hsio_pll_unprepare,
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.is_prepared = clk_hsio_pll_is_prepared,
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.recalc_rate = clk_hsio_pll_recalc_rate,
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};
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static int imx8mp_hsio_blk_ctrl_probe(struct imx8mp_blk_ctrl *bc)
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{
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struct clk_hsio_pll *clk_hsio_pll;
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struct clk_hw *hw;
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struct clk_init_data init = {};
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int ret;
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clk_hsio_pll = devm_kzalloc(bc->dev, sizeof(*clk_hsio_pll), GFP_KERNEL);
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if (!clk_hsio_pll)
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return -ENOMEM;
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init.name = "hsio_pll";
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init.ops = &clk_hsio_pll_ops;
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init.parent_names = (const char *[]){"osc_24m"};
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init.num_parents = 1;
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clk_hsio_pll->regmap = bc->regmap;
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clk_hsio_pll->hw.init = &init;
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hw = &clk_hsio_pll->hw;
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ret = devm_clk_hw_register(bc->dev, hw);
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if (ret)
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return ret;
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return devm_of_clk_add_hw_provider(bc->dev, of_clk_hw_simple_get, hw);
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}
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static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
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struct imx8mp_blk_ctrl_domain *domain)
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{
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@ -188,6 +285,7 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = {
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static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
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.max_reg = 0x24,
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.probe = imx8mp_hsio_blk_ctrl_probe,
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.power_on = imx8mp_hsio_blk_ctrl_power_on,
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.power_off = imx8mp_hsio_blk_ctrl_power_off,
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.power_notifier_fn = imx8mp_hsio_power_notifier,
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