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Merge branch 'linux-4.10' of git://github.com/skeggsb/linux into drm-next

Browse Source 
- Regression fix from atomic conversion (rotation on the original G80).
- Concurrency fix when clearing compression tags.
- Fixes DP link training issues on GP102/4/6.
- Fixes backlight handling in the presence of Apple GMUX.
- Improvements to GPU error recovery in a number of scenarios.
- GP106 support.

* 'linux-4.10' of git://github.com/skeggsb/linux:
  drm/nouveau/kms/nv50: fix atomic regression on original G80
  drm/nouveau/bl: Do not register interface if Apple GMUX detected
  drm/nouveau/bl: Assign different names to interfaces
  drm/nouveau/bios/dp: fix handling of LevelEntryTableIndex on DP table 4.2
  drm/nouveau/ltc: protect clearing of comptags with mutex
  drm/nouveau/gr/gf100-: handle GPC/TPC/MPC trap
  drm/nouveau/core: recognise GP106 chipset
  drm/nouveau/ttm: wait for bo fence to signal before unmapping vmas
  drm/nouveau/gr/gf100-: FECS intr handling is not relevant on proprietary ucode
  drm/nouveau/gr/gf100-: properly ack all FECS error interrupts
  drm/nouveau/fifo/gf100-: recover from host mmu faults
This commit is contained in:
Dave Airlie 2016-12-13 14:29:05 +10:00
commit 2cf026ae85
14 changed files with 172 additions and 39 deletions
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82
drivers/gpu/drm/nouveau/nouveau_backlight.c
View File

@ -30,12 +30,37 @@
* Register locations derived from NVClock by Roderick Colenbrander
*/
#include <linux/apple-gmux.h>
#include <linux/backlight.h>
#include <linux/idr.h>
#include "nouveau_drv.h"
#include "nouveau_reg.h"
#include "nouveau_encoder.h"
static struct ida bl_ida;
#define BL_NAME_SIZE 15 // 12 for name + 2 for digits + 1 for '\0'
struct backlight_connector {
struct list_head head;
int id;
};
static bool
nouveau_get_backlight_name(char backlight_name[BL_NAME_SIZE], struct backlight_connector
*connector)
{
const int nb = ida_simple_get(&bl_ida, 0, 0, GFP_KERNEL);
if (nb < 0 || nb >= 100)
return false;
if (nb > 0)
snprintf(backlight_name, BL_NAME_SIZE, "nv_backlight%d", nb);
else
snprintf(backlight_name, BL_NAME_SIZE, "nv_backlight");
connector->id = nb;
return true;
}
static int
nv40_get_intensity(struct backlight_device *bd)
{
@ -74,6 +99,8 @@ nv40_backlight_init(struct drm_connector *connector)
struct nvif_object *device = &drm->device.object;
struct backlight_properties props;
struct backlight_device *bd;
struct backlight_connector bl_connector;
char backlight_name[BL_NAME_SIZE];
if (!(nvif_rd32(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK))
return 0;
@ -81,10 +108,19 @@ nv40_backlight_init(struct drm_connector *connector)
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = 31;
bd = backlight_device_register("nv_backlight", connector->kdev, drm,
if (!nouveau_get_backlight_name(backlight_name, &bl_connector)) {
NV_ERROR(drm, "Failed to retrieve a unique name for the backlight interface\n");
return 0;
}
bd = backlight_device_register(backlight_name , connector->kdev, drm,
&nv40_bl_ops, &props);
if (IS_ERR(bd))
if (IS_ERR(bd)) {
if (bl_connector.id > 0)
ida_simple_remove(&bl_ida, bl_connector.id);
return PTR_ERR(bd);
}
list_add(&bl_connector.head, &drm->bl_connectors);
drm->backlight = bd;
bd->props.brightness = nv40_get_intensity(bd);
backlight_update_status(bd);
@ -182,6 +218,8 @@ nv50_backlight_init(struct drm_connector *connector)
struct backlight_properties props;
struct backlight_device *bd;
const struct backlight_ops *ops;
struct backlight_connector bl_connector;
char backlight_name[BL_NAME_SIZE];
nv_encoder = find_encoder(connector, DCB_OUTPUT_LVDS);
if (!nv_encoder) {
@ -203,11 +241,20 @@ nv50_backlight_init(struct drm_connector *connector)
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = 100;
bd = backlight_device_register("nv_backlight", connector->kdev,
if (!nouveau_get_backlight_name(backlight_name, &bl_connector)) {
NV_ERROR(drm, "Failed to retrieve a unique name for the backlight interface\n");
return 0;
}
bd = backlight_device_register(backlight_name , connector->kdev,
nv_encoder, ops, &props);
if (IS_ERR(bd))
return PTR_ERR(bd);
if (IS_ERR(bd)) {
if (bl_connector.id > 0)
ida_simple_remove(&bl_ida, bl_connector.id);
return PTR_ERR(bd);
}
list_add(&bl_connector.head, &drm->bl_connectors);
drm->backlight = bd;
bd->props.brightness = bd->ops->get_brightness(bd);
backlight_update_status(bd);
@ -221,6 +268,13 @@ nouveau_backlight_init(struct drm_device *dev)
struct nvif_device *device = &drm->device;
struct drm_connector *connector;
if (apple_gmux_present()) {
NV_INFO(drm, "Apple GMUX detected: not registering Nouveau backlight interface\n");
return 0;
}
INIT_LIST_HEAD(&drm->bl_connectors);
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS &&
connector->connector_type != DRM_MODE_CONNECTOR_eDP)
@ -247,9 +301,27 @@ void
nouveau_backlight_exit(struct drm_device *dev)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct backlight_connector *connector;
list_for_each_entry(connector, &drm->bl_connectors, head) {
if (connector->id >= 0)
ida_simple_remove(&bl_ida, connector->id);
}
if (drm->backlight) {
backlight_device_unregister(drm->backlight);
drm->backlight = NULL;
}
}
void
nouveau_backlight_ctor(void)
{
ida_init(&bl_ida);
}
void
nouveau_backlight_dtor(void)
{
ida_destroy(&bl_ida);
}

1
drivers/gpu/drm/nouveau/nouveau_bo.c
View File

@ -1209,6 +1209,7 @@ nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
nvbo->page_shift != vma->vm->mmu->lpg_shift)) {
nvkm_vm_map(vma, new_mem->mm_node);
} else {
WARN_ON(ttm_bo_wait(bo, false, false));
nvkm_vm_unmap(vma);
}
}

10
drivers/gpu/drm/nouveau/nouveau_display.h
View File

@ -91,6 +91,8 @@ int nouveau_crtc_set_config(struct drm_mode_set *set);
#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
extern int nouveau_backlight_init(struct drm_device *);
extern void nouveau_backlight_exit(struct drm_device *);
extern void nouveau_backlight_ctor(void);
extern void nouveau_backlight_dtor(void);
#else
static inline int
nouveau_backlight_init(struct drm_device *dev)
@ -101,6 +103,14 @@ nouveau_backlight_init(struct drm_device *dev)
static inline void
nouveau_backlight_exit(struct drm_device *dev) {
}
static inline void
nouveau_backlight_ctor(void) {
}
static inline void
nouveau_backlight_dtor(void) {
}
#endif
struct drm_framebuffer *

2
drivers/gpu/drm/nouveau/nouveau_drm.c
View File

@ -1122,6 +1122,7 @@ nouveau_drm_init(void)
#endif
nouveau_register_dsm_handler();
nouveau_backlight_ctor();
return drm_pci_init(&driver_pci, &nouveau_drm_pci_driver);
}
@ -1132,6 +1133,7 @@ nouveau_drm_exit(void)
return;
drm_pci_exit(&driver_pci, &nouveau_drm_pci_driver);
nouveau_backlight_dtor();
nouveau_unregister_dsm_handler();
#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER

1
drivers/gpu/drm/nouveau/nouveau_drv.h
View File

@ -163,6 +163,7 @@ struct nouveau_drm {
struct nvbios vbios;
struct nouveau_display *display;
struct backlight_device *backlight;
struct list_head bl_connectors;
struct work_struct hpd_work;
#ifdef CONFIG_ACPI
struct notifier_block acpi_nb;

5
drivers/gpu/drm/nouveau/nv50_display.c
View File

@ -1726,6 +1726,11 @@ nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
evo_data(push, asyh->core.handle);
evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
evo_data(push, (asyh->core.y << 16) | asyh->core.x);
/* EVO will complain with INVALID_STATE if we have an
* active cursor and (re)specify HeadSetContextDmaIso
* without also updating HeadSetOffsetCursor.
*/
asyh->set.curs = asyh->curs.visible;
} else
if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);

30
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -2241,6 +2241,35 @@ nv134_chipset = {
.fifo = gp100_fifo_new,
};
static const struct nvkm_device_chip
nv136_chipset = {
.name = "GP106",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.devinit = gm200_devinit_new,
.fb = gp102_fb_new,
.fuse = gm107_fuse_new,
.gpio = gk104_gpio_new,
.i2c = gm200_i2c_new,
.ibus = gm200_ibus_new,
.imem = nv50_instmem_new,
.ltc = gp100_ltc_new,
.mc = gp100_mc_new,
.mmu = gf100_mmu_new,
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
.timer = gk20a_timer_new,
.top = gk104_top_new,
.ce[0] = gp102_ce_new,
.ce[1] = gp102_ce_new,
.ce[2] = gp102_ce_new,
.ce[3] = gp102_ce_new,
.disp = gp102_disp_new,
.dma = gf119_dma_new,
.fifo = gp100_fifo_new,
};
static int
nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size,
struct nvkm_notify *notify)
@ -2677,6 +2706,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
case 0x130: device->chip = &nv130_chipset; break;
case 0x132: device->chip = &nv132_chipset; break;
case 0x134: device->chip = &nv134_chipset; break;
case 0x136: device->chip = &nv136_chipset; break;
default:
nvdev_error(device, "unknown chipset (%08x)\n", boot0);
goto done;

3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
View File

@ -180,7 +180,8 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
list_del_init(&chan->head);
chan->killed = true;
fifo->recover.mask |= 1ULL << engine->subdev.index;
if (engine != &fifo->base.engine)
fifo->recover.mask |= 1ULL << engine->subdev.index;
schedule_work(&fifo->recover.work);
}

16
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
View File

@ -743,14 +743,14 @@ gk104_fifo_fault_engine[] = {
{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
{ 0x06, "SCHED" },
{ 0x07, "HOST0" },
{ 0x08, "HOST1" },
{ 0x09, "HOST2" },
{ 0x0a, "HOST3" },
{ 0x0b, "HOST4" },
{ 0x0c, "HOST5" },
{ 0x0d, "HOST6" },
{ 0x0e, "HOST7" },
{ 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO },
{ 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO },
{ 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO },
{ 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO },
{ 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO },
{ 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO },
{ 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO },
{ 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO },
{ 0x0f, "HOSTSR" },
{ 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD },
{ 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP },

16
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
View File

@ -32,14 +32,14 @@ gm107_fifo_fault_engine[] = {
{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
{ 0x06, "SCHED" },
{ 0x07, "HOST0" },
{ 0x08, "HOST1" },
{ 0x09, "HOST2" },
{ 0x0a, "HOST3" },
{ 0x0b, "HOST4" },
{ 0x0c, "HOST5" },
{ 0x0d, "HOST6" },
{ 0x0e, "HOST7" },
{ 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO },
{ 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO },
{ 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO },
{ 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO },
{ 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO },
{ 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO },
{ 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO },
{ 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO },
{ 0x0f, "HOSTSR" },
{ 0x13, "PERF" },
{ 0x17, "PMU" },

22
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c
View File

@ -30,17 +30,17 @@ gp100_fifo_fault_engine[] = {
{ 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
{ 0x06, "HOST0" },
{ 0x07, "HOST1" },
{ 0x08, "HOST2" },
{ 0x09, "HOST3" },
{ 0x0a, "HOST4" },
{ 0x0b, "HOST5" },
{ 0x0c, "HOST6" },
{ 0x0d, "HOST7" },
{ 0x0e, "HOST8" },
{ 0x0f, "HOST9" },
{ 0x10, "HOST10" },
{ 0x06, "HOST0", NULL, NVKM_ENGINE_FIFO },
{ 0x07, "HOST1", NULL, NVKM_ENGINE_FIFO },
{ 0x08, "HOST2", NULL, NVKM_ENGINE_FIFO },
{ 0x09, "HOST3", NULL, NVKM_ENGINE_FIFO },
{ 0x0a, "HOST4", NULL, NVKM_ENGINE_FIFO },
{ 0x0b, "HOST5", NULL, NVKM_ENGINE_FIFO },
{ 0x0c, "HOST6", NULL, NVKM_ENGINE_FIFO },
{ 0x0d, "HOST7", NULL, NVKM_ENGINE_FIFO },
{ 0x0e, "HOST8", NULL, NVKM_ENGINE_FIFO },
{ 0x0f, "HOST9", NULL, NVKM_ENGINE_FIFO },
{ 0x10, "HOST10", NULL, NVKM_ENGINE_FIFO },
{ 0x13, "PERF" },
{ 0x17, "PMU" },
{ 0x18, "PTP" },

16
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -1041,6 +1041,13 @@ gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
stat &= ~0x00000008;
}
if (stat & 0x00000010) {
u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430));
nvkm_error(subdev, "GPC%d/TPC%d/MPC: %08x\n", gpc, tpc, trap);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000);
stat &= ~0x00000010;
}
if (stat) {
nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat);
}
@ -1258,7 +1265,7 @@ gf100_gr_ctxctl_isr(struct gf100_gr *gr)
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x409c18);
if (stat & 0x00000001) {
if (!gr->firmware && (stat & 0x00000001)) {
u32 code = nvkm_rd32(device, 0x409814);
if (code == E_BAD_FWMTHD) {
u32 class = nvkm_rd32(device, 0x409808);
@ -1270,15 +1277,14 @@ gf100_gr_ctxctl_isr(struct gf100_gr *gr)
nvkm_error(subdev, "FECS MTHD subc %d class %04x "
"mthd %04x data %08x\n",
subc, class, mthd, data);
nvkm_wr32(device, 0x409c20, 0x00000001);
stat &= ~0x00000001;
} else {
nvkm_error(subdev, "FECS ucode error %d\n", code);
}
nvkm_wr32(device, 0x409c20, 0x00000001);
stat &= ~0x00000001;
}
if (stat & 0x00080000) {
if (!gr->firmware && (stat & 0x00080000)) {
nvkm_error(subdev, "FECS watchdog timeout\n");
gf100_gr_ctxctl_debug(gr);
nvkm_wr32(device, 0x409c20, 0x00080000);

5
drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c
View File

@ -207,8 +207,11 @@ nvbios_dpcfg_match(struct nvkm_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,
if (*ver >= 0x30) {
const u8 vsoff[] = { 0, 4, 7, 9 };
idx = (pc * 10) + vsoff[vs] + pe;
if (*ver >= 0x40 && *hdr >= 0x12)
if (*ver >= 0x40 && *ver <= 0x41 && *hdr >= 0x12)
idx += nvbios_rd08(bios, outp + 0x11) * 40;
else
if (*ver >= 0x42)
idx += nvbios_rd08(bios, outp + 0x11) * 10;
} else {
while ((data = nvbios_dpcfg_entry(bios, outp, ++idx,
ver, hdr, cnt, len))) {

2
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c
View File

@ -47,8 +47,10 @@ nvkm_ltc_tags_clear(struct nvkm_ltc *ltc, u32 first, u32 count)
BUG_ON((first > limit) || (limit >= ltc->num_tags));
mutex_lock(&ltc->subdev.mutex);
ltc->func->cbc_clear(ltc, first, limit);
ltc->func->cbc_wait(ltc);
mutex_unlock(&ltc->subdev.mutex);
}
int