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drm/i915/tc: Clear DKL_TX_PMD_LANE_SUS before program voltage swing

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This sequence was recently added to fix internal HW sequences to
reset TC ports.

HSDES: 1507287614
HSDES: 14010071447
BSpec: 49292
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191021223408.87344-1-jose.souza@intel.com
This commit is contained in:
José Roberto de Souza 2019-10-21 15:34:08 -07:00
parent c442292a66
commit 2d69c42e37
2 changed files with 8 additions and 0 deletions
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2
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@ -2838,6 +2838,8 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
for (ln = 0; ln < 2; ln++) {
I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
I915_WRITE(DKL_TX_PMD_LANE_SUS(tc_port), 0);
/* All the registers are RMW */
val = I915_READ(DKL_TX_DPCNTL0(tc_port));
val &= ~dpcnt_mask;

6
drivers/gpu/drm/i915/i915_reg.h
View File

@ -10260,6 +10260,12 @@ enum skl_power_gate {
_DKL_PHY2_BASE) + \
_DKL_TX_FW_CALIB)
#define _DKL_TX_PMD_LANE_SUS 0xD00
#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
_DKL_PHY1_BASE, \
_DKL_PHY2_BASE) + \
_DKL_TX_PMD_LANE_SUS)
#define _DKL_TX_DW17 0xDC4
#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
_DKL_PHY1_BASE, \