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bpf: interpreter support BPF_ALU | BPF_ARSH

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This patch implements interpreting BPF_ALU | BPF_ARSH. Do arithmetic right
shift on low 32-bit sub-register, and zero the high 32 bits.

Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
This commit is contained in:
Jiong Wang 2018-12-05 13:52:34 -05:00 committed by Alexei Starovoitov
parent 84708c1386
commit 2dc6b100f9
1 changed files with 30 additions and 22 deletions
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52
kernel/bpf/core.c
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@ -933,32 +933,34 @@ EXPORT_SYMBOL_GPL(__bpf_call_base);
#define BPF_INSN_MAP(INSN_2, INSN_3) \ #define BPF_INSN_MAP(INSN_2, INSN_3) \
/* 32 bit ALU operations. */ \ /* 32 bit ALU operations. */ \
/* Register based. */ \ /* Register based. */ \
INSN_3(ALU, ADD, X), \ INSN_3(ALU, ADD, X), \
INSN_3(ALU, SUB, X), \ INSN_3(ALU, SUB, X), \
INSN_3(ALU, AND, X), \ INSN_3(ALU, AND, X), \
INSN_3(ALU, OR, X), \ INSN_3(ALU, OR, X), \
INSN_3(ALU, LSH, X), \ INSN_3(ALU, LSH, X), \
INSN_3(ALU, RSH, X), \ INSN_3(ALU, RSH, X), \
INSN_3(ALU, XOR, X), \ INSN_3(ALU, XOR, X), \
INSN_3(ALU, MUL, X), \ INSN_3(ALU, MUL, X), \
INSN_3(ALU, MOV, X), \ INSN_3(ALU, MOV, X), \
INSN_3(ALU, DIV, X), \ INSN_3(ALU, ARSH, X), \
INSN_3(ALU, MOD, X), \ INSN_3(ALU, DIV, X), \
INSN_3(ALU, MOD, X), \
INSN_2(ALU, NEG), \ INSN_2(ALU, NEG), \
INSN_3(ALU, END, TO_BE), \ INSN_3(ALU, END, TO_BE), \
INSN_3(ALU, END, TO_LE), \ INSN_3(ALU, END, TO_LE), \
/* Immediate based. */ \ /* Immediate based. */ \
INSN_3(ALU, ADD, K), \ INSN_3(ALU, ADD, K), \
INSN_3(ALU, SUB, K), \ INSN_3(ALU, SUB, K), \
INSN_3(ALU, AND, K), \ INSN_3(ALU, AND, K), \
INSN_3(ALU, OR, K), \ INSN_3(ALU, OR, K), \
INSN_3(ALU, LSH, K), \ INSN_3(ALU, LSH, K), \
INSN_3(ALU, RSH, K), \ INSN_3(ALU, RSH, K), \
INSN_3(ALU, XOR, K), \ INSN_3(ALU, XOR, K), \
INSN_3(ALU, MUL, K), \ INSN_3(ALU, MUL, K), \
INSN_3(ALU, MOV, K), \ INSN_3(ALU, MOV, K), \
INSN_3(ALU, DIV, K), \ INSN_3(ALU, ARSH, K), \
INSN_3(ALU, MOD, K), \ INSN_3(ALU, DIV, K), \
INSN_3(ALU, MOD, K), \
/* 64 bit ALU operations. */ \ /* 64 bit ALU operations. */ \
/* Register based. */ \ /* Register based. */ \
INSN_3(ALU64, ADD, X), \ INSN_3(ALU64, ADD, X), \
@ -1137,6 +1139,12 @@ select_insn:
DST = (u64) (u32) insn[0].imm | ((u64) (u32) insn[1].imm) << 32; DST = (u64) (u32) insn[0].imm | ((u64) (u32) insn[1].imm) << 32;
insn++; insn++;
CONT; CONT;
ALU_ARSH_X:
DST = (u64) (u32) ((*(s32 *) &DST) >> SRC);
CONT;
ALU_ARSH_K:
DST = (u64) (u32) ((*(s32 *) &DST) >> IMM);
CONT;
ALU64_ARSH_X: ALU64_ARSH_X:
(*(s64 *) &DST) >>= SRC; (*(s64 *) &DST) >>= SRC;
CONT; CONT;