KVM: riscv: selftests: Add vector crypto extensions to get-reg-list test
The KVM RISC-V allows vector crypto extensions for Guest/VM so let us add these extensions to get-reg-list test. This includes extensions Zvbb, Zvbc, Zvkb, Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh, and Zvkt. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
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@ -69,6 +69,16 @@ bool filter_reg(__u64 reg)
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSED:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSH:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKT:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKG:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNED:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHA:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHB:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSED:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSH:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKT:
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/*
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* Like ISA_EXT registers, SBI_EXT registers are only visible when the
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* host supports them and disabling them does not affect the visibility
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@ -425,6 +435,16 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
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KVM_ISA_EXT_ARR(ZKSED),
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KVM_ISA_EXT_ARR(ZKSH),
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KVM_ISA_EXT_ARR(ZKT),
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KVM_ISA_EXT_ARR(ZVBB),
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KVM_ISA_EXT_ARR(ZVBC),
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KVM_ISA_EXT_ARR(ZVKB),
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KVM_ISA_EXT_ARR(ZVKG),
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KVM_ISA_EXT_ARR(ZVKNED),
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KVM_ISA_EXT_ARR(ZVKNHA),
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KVM_ISA_EXT_ARR(ZVKNHB),
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KVM_ISA_EXT_ARR(ZVKSED),
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KVM_ISA_EXT_ARR(ZVKSH),
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KVM_ISA_EXT_ARR(ZVKT),
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};
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if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name))
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@ -930,6 +950,16 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zkr, ZKR);
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KVM_ISA_EXT_SIMPLE_CONFIG(zksed, ZKSED);
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KVM_ISA_EXT_SIMPLE_CONFIG(zksh, ZKSH);
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KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT);
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KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB);
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KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC);
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KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB);
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KVM_ISA_EXT_SIMPLE_CONFIG(zvkg, ZVKG);
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KVM_ISA_EXT_SIMPLE_CONFIG(zvkned, ZVKNED);
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KVM_ISA_EXT_SIMPLE_CONFIG(zvknha, ZVKNHA);
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KVM_ISA_EXT_SIMPLE_CONFIG(zvknhb, ZVKNHB);
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KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED);
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KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH);
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KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT);
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struct vcpu_reg_list *vcpu_configs[] = {
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&config_sbi_base,
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@ -967,5 +997,15 @@ struct vcpu_reg_list *vcpu_configs[] = {
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&config_zksed,
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&config_zksh,
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&config_zkt,
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&config_zvbb,
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&config_zvbc,
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&config_zvkb,
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&config_zvkg,
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&config_zvkned,
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&config_zvknha,
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&config_zvknhb,
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&config_zvksed,
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&config_zvksh,
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&config_zvkt,
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};
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int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);
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