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ARM: S5P: Cleanup S5P gpio interrupt code

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This patch performs a global cleanup in s5p gpio interrupt support code.
The code is prepared for upcoming support for gpio interrupts on EXYNOS4
platform, which has 2 gpio banks (regions) instead of one (like on
S5PC110 and S5PC100).

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Marek Szyprowski 2011-03-15 21:17:43 +09:00 committed by Kukjin Kim
parent 47a9c0ee79
commit 2de0926204
1 changed files with 46 additions and 60 deletions
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104
arch/arm/plat-s5p/irq-gpioint.c
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@ -22,77 +22,64 @@
#include <plat/gpio-core.h> #include <plat/gpio-core.h>
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x)) #define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u)
#define GPIOINT_CON_OFFSET 0x700 #define CON_OFFSET 0x700
#define GPIOINT_MASK_OFFSET 0x900 #define MASK_OFFSET 0x900
#define GPIOINT_PEND_OFFSET 0xA00 #define PEND_OFFSET 0xA00
#define REG_OFFSET(x) ((x) << 2)
static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR]; static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR];
static int s5p_gpioint_get_group(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_data(data);
struct s3c_gpio_chip *s3c_chip = container_of(chip,
struct s3c_gpio_chip, chip);
int group;
for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++)
if (s3c_chip == irq_chips[group])
break;
return group;
}
static int s5p_gpioint_get_offset(struct irq_data *data) static int s5p_gpioint_get_offset(struct irq_data *data)
{ {
struct gpio_chip *chip = irq_data_get_irq_data(data); struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
struct s3c_gpio_chip *s3c_chip = container_of(chip, return data->irq - chip->irq_base;
struct s3c_gpio_chip, chip);
return data->irq - s3c_chip->irq_base;
} }
static void s5p_gpioint_ack(struct irq_data *data) static void s5p_gpioint_ack(struct irq_data *data)
{ {
struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
int group, offset, pend_offset; int group, offset, pend_offset;
unsigned int value; unsigned int value;
group = s5p_gpioint_get_group(data); group = chip->group;
offset = s5p_gpioint_get_offset(data); offset = s5p_gpioint_get_offset(data);
pend_offset = group << 2; pend_offset = REG_OFFSET(group);
value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset); value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
value |= 1 << offset; value |= BIT(offset);
__raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset); __raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
} }
static void s5p_gpioint_mask(struct irq_data *data) static void s5p_gpioint_mask(struct irq_data *data)
{ {
struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
int group, offset, mask_offset; int group, offset, mask_offset;
unsigned int value; unsigned int value;
group = s5p_gpioint_get_group(data); group = chip->group;
offset = s5p_gpioint_get_offset(data); offset = s5p_gpioint_get_offset(data);
mask_offset = group << 2; mask_offset = REG_OFFSET(group);
value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
value |= 1 << offset; value |= BIT(offset);
__raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
} }
static void s5p_gpioint_unmask(struct irq_data *data) static void s5p_gpioint_unmask(struct irq_data *data)
{ {
struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
int group, offset, mask_offset; int group, offset, mask_offset;
unsigned int value; unsigned int value;
group = s5p_gpioint_get_group(data); group = chip->group;
offset = s5p_gpioint_get_offset(data); offset = s5p_gpioint_get_offset(data);
mask_offset = group << 2; mask_offset = REG_OFFSET(group);
value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
value &= ~(1 << offset); value &= ~BIT(offset);
__raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
} }
static void s5p_gpioint_mask_ack(struct irq_data *data) static void s5p_gpioint_mask_ack(struct irq_data *data)
@ -103,12 +90,13 @@ static void s5p_gpioint_mask_ack(struct irq_data *data)
static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
{ {
struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
int group, offset, con_offset; int group, offset, con_offset;
unsigned int value; unsigned int value;
group = s5p_gpioint_get_group(data); group = chip->group;
offset = s5p_gpioint_get_offset(data); offset = s5p_gpioint_get_offset(data);
con_offset = group << 2; con_offset = REG_OFFSET(group);
switch (type) { switch (type) {
case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_EDGE_RISING:
@ -132,15 +120,15 @@ static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
return -EINVAL; return -EINVAL;
} }
value = __raw_readl(S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset); value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset);
value &= ~(0x7 << (offset * 0x4)); value &= ~(0x7 << (offset * 0x4));
value |= (type << (offset * 0x4)); value |= (type << (offset * 0x4));
__raw_writel(value, S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset); __raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset);
return 0; return 0;
} }
struct irq_chip s5p_gpioint = { static struct irq_chip s5p_gpioint = {
.name = "s5p_gpioint", .name = "s5p_gpioint",
.irq_ack = s5p_gpioint_ack, .irq_ack = s5p_gpioint_ack,
.irq_mask = s5p_gpioint_mask, .irq_mask = s5p_gpioint_mask,
@ -151,30 +139,28 @@ struct irq_chip s5p_gpioint = {
static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
{ {
int group, offset, pend_offset, mask_offset; int group, pend_offset, mask_offset;
int real_irq;
unsigned int pend, mask; unsigned int pend, mask;
for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++) { for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++) {
pend_offset = group << 2; struct s3c_gpio_chip *chip = irq_chips[group];
pend = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + if (!chip)
pend_offset); continue;
pend_offset = REG_OFFSET(group);
pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
if (!pend) if (!pend)
continue; continue;
mask_offset = group << 2; mask_offset = REG_OFFSET(group);
mask = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
mask_offset);
pend &= ~mask; pend &= ~mask;
for (offset = 0; offset < 8; offset++) { while (pend) {
if (pend & (1 << offset)) { int offset = fls(pend) - 1;
struct s3c_gpio_chip *chip = irq_chips[group]; int real_irq = chip->irq_base + offset;
if (chip) {
real_irq = chip->irq_base + offset;
generic_handle_irq(real_irq); generic_handle_irq(real_irq);
} pend &= ~BIT(offset);
}
} }
} }
} }
@ -202,7 +188,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
for (i = 0; i < chip->chip.ngpio; i++) { for (i = 0; i < chip->chip.ngpio; i++) {
irq = chip->irq_base + i; irq = chip->irq_base + i;
set_irq_chip(irq, &s5p_gpioint); set_irq_chip(irq, &s5p_gpioint);
set_irq_data(irq, &chip->chip); set_irq_data(irq, chip);
set_irq_handler(irq, handle_level_irq); set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }