i40e: Add support for X710 B/P & SFP+ cards
New device ids are created to support X710 backplane and SFP+ cards. This patch adds in i40e driver support for 2.5GbaseT and 5GbaseT speed. It's implemented by checking I40E_CAP_PHY_TYPE_2_5GBASE_T, I40E_CAP_PHY_TYPE_5GBASE_T bits from f/w and setting corresponding bits in ethtool link ksettings supported and advertising masks. Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Signed-off-by: Alice Michael <alice.michael@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -1888,6 +1888,8 @@ enum i40e_aq_phy_type {
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I40E_PHY_TYPE_25GBASE_LR = 0x22,
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I40E_PHY_TYPE_25GBASE_AOC = 0x23,
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I40E_PHY_TYPE_25GBASE_ACC = 0x24,
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I40E_PHY_TYPE_2_5GBASE_T = 0x30,
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I40E_PHY_TYPE_5GBASE_T = 0x31,
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I40E_PHY_TYPE_MAX,
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I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
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I40E_PHY_TYPE_EMPTY = 0xFE,
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@ -1929,19 +1931,25 @@ enum i40e_aq_phy_type {
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BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
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BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
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BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
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BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC))
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BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
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BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
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BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
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#define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
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#define I40E_LINK_SPEED_100MB_SHIFT 0x1
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#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
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#define I40E_LINK_SPEED_10GB_SHIFT 0x3
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#define I40E_LINK_SPEED_40GB_SHIFT 0x4
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#define I40E_LINK_SPEED_20GB_SHIFT 0x5
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#define I40E_LINK_SPEED_25GB_SHIFT 0x6
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#define I40E_LINK_SPEED_5GB_SHIFT 0x7
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enum i40e_aq_link_speed {
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I40E_LINK_SPEED_UNKNOWN = 0,
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I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
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I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
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I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
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I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT),
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I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
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I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
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I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT),
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@ -1987,6 +1995,8 @@ struct i40e_aq_get_phy_abilities_resp {
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#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
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#define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10
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#define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20
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#define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40
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#define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80
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u8 fec_cfg_curr_mod_ext_info;
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#define I40E_AQ_ENABLE_FEC_KR 0x01
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#define I40E_AQ_ENABLE_FEC_RS 0x02
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@ -28,6 +28,8 @@ static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
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case I40E_DEV_ID_QSFP_C:
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case I40E_DEV_ID_10G_BASE_T:
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case I40E_DEV_ID_10G_BASE_T4:
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case I40E_DEV_ID_10G_B:
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case I40E_DEV_ID_10G_SFP:
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case I40E_DEV_ID_20G_KR2:
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case I40E_DEV_ID_20G_KR2_A:
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case I40E_DEV_ID_25G_B:
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@ -1151,6 +1153,8 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
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break;
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case I40E_PHY_TYPE_100BASE_TX:
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case I40E_PHY_TYPE_1000BASE_T:
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case I40E_PHY_TYPE_2_5GBASE_T:
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case I40E_PHY_TYPE_5GBASE_T:
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case I40E_PHY_TYPE_10GBASE_T:
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media = I40E_MEDIA_TYPE_BASET;
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break;
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@ -4900,6 +4904,7 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,
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break;
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case I40E_DEV_ID_10G_BASE_T:
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case I40E_DEV_ID_10G_BASE_T4:
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case I40E_DEV_ID_10G_BASE_T_BC:
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case I40E_DEV_ID_10G_BASE_T_X722:
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case I40E_DEV_ID_25G_B:
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case I40E_DEV_ID_25G_SFP28:
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@ -20,6 +20,9 @@
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#define I40E_DEV_ID_10G_BASE_T4 0x1589
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#define I40E_DEV_ID_25G_B 0x158A
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#define I40E_DEV_ID_25G_SFP28 0x158B
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#define I40E_DEV_ID_10G_BASE_T_BC 0x15FF
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#define I40E_DEV_ID_10G_B 0x104F
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#define I40E_DEV_ID_10G_SFP 0x104E
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#define I40E_DEV_ID_KX_X722 0x37CE
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#define I40E_DEV_ID_QSFP_X722 0x37CF
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#define I40E_DEV_ID_SFP_X722 0x37D0
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@ -508,6 +508,20 @@ static void i40e_phy_type_to_ethtool(struct i40e_pf *pf,
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ethtool_link_ksettings_add_link_mode(ks, advertising,
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10000baseT_Full);
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}
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if (phy_types & I40E_CAP_PHY_TYPE_2_5GBASE_T) {
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ethtool_link_ksettings_add_link_mode(ks, supported,
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2500baseT_Full);
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if (hw_link_info->requested_speeds & I40E_LINK_SPEED_2_5GB)
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ethtool_link_ksettings_add_link_mode(ks, advertising,
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2500baseT_Full);
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}
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if (phy_types & I40E_CAP_PHY_TYPE_5GBASE_T) {
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ethtool_link_ksettings_add_link_mode(ks, supported,
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5000baseT_Full);
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if (hw_link_info->requested_speeds & I40E_LINK_SPEED_5GB)
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ethtool_link_ksettings_add_link_mode(ks, advertising,
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5000baseT_Full);
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}
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if (phy_types & I40E_CAP_PHY_TYPE_XLAUI ||
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phy_types & I40E_CAP_PHY_TYPE_XLPPI ||
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phy_types & I40E_CAP_PHY_TYPE_40GBASE_AOC)
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@ -674,13 +688,15 @@ static void i40e_phy_type_to_ethtool(struct i40e_pf *pf,
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phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||
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phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR ||
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phy_types & I40E_CAP_PHY_TYPE_20GBASE_KR2 ||
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phy_types & I40E_CAP_PHY_TYPE_10GBASE_T ||
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phy_types & I40E_CAP_PHY_TYPE_10GBASE_SR ||
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phy_types & I40E_CAP_PHY_TYPE_10GBASE_LR ||
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phy_types & I40E_CAP_PHY_TYPE_10GBASE_KX4 ||
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phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR ||
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phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1_CU ||
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phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1 ||
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phy_types & I40E_CAP_PHY_TYPE_10GBASE_T ||
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phy_types & I40E_CAP_PHY_TYPE_5GBASE_T ||
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phy_types & I40E_CAP_PHY_TYPE_2_5GBASE_T ||
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phy_types & I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL ||
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phy_types & I40E_CAP_PHY_TYPE_1000BASE_T ||
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phy_types & I40E_CAP_PHY_TYPE_1000BASE_SX ||
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@ -790,11 +806,17 @@ static void i40e_get_settings_link_up(struct i40e_hw *hw,
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10000baseT_Full);
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break;
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case I40E_PHY_TYPE_10GBASE_T:
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case I40E_PHY_TYPE_5GBASE_T:
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case I40E_PHY_TYPE_2_5GBASE_T:
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case I40E_PHY_TYPE_1000BASE_T:
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case I40E_PHY_TYPE_100BASE_TX:
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ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
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ethtool_link_ksettings_add_link_mode(ks, supported,
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10000baseT_Full);
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ethtool_link_ksettings_add_link_mode(ks, supported,
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5000baseT_Full);
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ethtool_link_ksettings_add_link_mode(ks, supported,
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2500baseT_Full);
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ethtool_link_ksettings_add_link_mode(ks, supported,
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1000baseT_Full);
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ethtool_link_ksettings_add_link_mode(ks, supported,
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@ -803,6 +825,12 @@ static void i40e_get_settings_link_up(struct i40e_hw *hw,
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if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
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ethtool_link_ksettings_add_link_mode(ks, advertising,
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10000baseT_Full);
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if (hw_link_info->requested_speeds & I40E_LINK_SPEED_5GB)
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ethtool_link_ksettings_add_link_mode(ks, advertising,
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5000baseT_Full);
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if (hw_link_info->requested_speeds & I40E_LINK_SPEED_2_5GB)
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ethtool_link_ksettings_add_link_mode(ks, advertising,
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2500baseT_Full);
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if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
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ethtool_link_ksettings_add_link_mode(ks, advertising,
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1000baseT_Full);
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@ -958,6 +986,12 @@ static void i40e_get_settings_link_up(struct i40e_hw *hw,
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case I40E_LINK_SPEED_10GB:
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ks->base.speed = SPEED_10000;
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break;
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case I40E_LINK_SPEED_5GB:
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ks->base.speed = SPEED_5000;
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break;
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case I40E_LINK_SPEED_2_5GB:
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ks->base.speed = SPEED_2500;
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break;
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case I40E_LINK_SPEED_1GB:
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ks->base.speed = SPEED_1000;
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break;
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@ -1243,6 +1277,12 @@ static int i40e_set_link_ksettings(struct net_device *netdev,
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ethtool_link_ksettings_test_link_mode(ks, advertising,
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10000baseLR_Full))
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config.link_speed |= I40E_LINK_SPEED_10GB;
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if (ethtool_link_ksettings_test_link_mode(ks, advertising,
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2500baseT_Full))
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config.link_speed |= I40E_LINK_SPEED_2_5GB;
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if (ethtool_link_ksettings_test_link_mode(ks, advertising,
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5000baseT_Full))
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config.link_speed |= I40E_LINK_SPEED_5GB;
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if (ethtool_link_ksettings_test_link_mode(ks, advertising,
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20000baseKR2_Full))
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config.link_speed |= I40E_LINK_SPEED_20GB;
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@ -73,6 +73,8 @@ static const struct pci_device_id i40e_pci_tbl[] = {
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{PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
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{PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
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{PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
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{PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_SFP), 0},
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{PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_B), 0},
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{PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
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{PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
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{PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
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@ -6520,6 +6522,12 @@ void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
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case I40E_LINK_SPEED_10GB:
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speed = "10 G";
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break;
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case I40E_LINK_SPEED_5GB:
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speed = "5 G";
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break;
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case I40E_LINK_SPEED_2_5GB:
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speed = "2.5 G";
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break;
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case I40E_LINK_SPEED_1GB:
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speed = "1000 M";
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break;
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@ -252,6 +252,12 @@ struct i40e_phy_info {
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I40E_PHY_TYPE_OFFSET)
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#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
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I40E_PHY_TYPE_OFFSET)
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/* Offset for 2.5G/5G PHY Types value to bit number conversion */
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#define I40E_PHY_TYPE_OFFSET2 (-10)
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#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
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I40E_PHY_TYPE_OFFSET2)
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#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
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I40E_PHY_TYPE_OFFSET2)
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#define I40E_HW_CAP_MAX_GPIO 30
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/* Capabilities of a PF or a VF or the whole device */
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struct i40e_hw_capabilities {
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