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arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems

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[ Upstream commit 8b6a006c91 ]

The GICv3 interrupts binding does not have a cpumask. The CPU mask only
applies to pre-GICv3. So just drop using them from GICv3 systems.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Stable-dep-of: 6fca24a07e ("arm64: dts: renesas: r8a779a0: Add missing hypervisor virtual timer IRQ")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Lad Prabhakar
2023-02-06 00:21:36 +00:00
committed by Greg Kroah-Hartman
parent 16d163f672
commit 2e74978052
9 changed files with 27 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@ -2209,8 +2209,7 @@
interrupt-controller; interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>, reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>; <0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
fcpvd0: fcp@fea10000 { fcpvd0: fcp@fea10000 {
@ -2857,9 +2856,9 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

11
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
View File

@ -935,8 +935,7 @@
interrupt-controller; interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>, reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>; <0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
prr: chipid@fff00044 { prr: chipid@fff00044 {
@ -991,10 +990,10 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
}; };
ufs30_clk: ufs30-clk { ufs30_clk: ufs30-clk {

11
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View File

@ -550,8 +550,7 @@
interrupt-controller; interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>, reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>; <0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
prr: chipid@fff00044 { prr: chipid@fff00044 {
@ -562,9 +561,9 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

8
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
View File

@ -41,10 +41,10 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

8
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@ -1091,9 +1091,9 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

7
arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
View File

@ -15,13 +15,6 @@
/delete-node/ cpu-map; /delete-node/ cpu-map;
/delete-node/ cpu@100; /delete-node/ cpu@100;
}; };
timer {
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
}; };
&soc { &soc {

7
arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
View File

@ -15,11 +15,4 @@
/delete-node/ cpu-map; /delete-node/ cpu-map;
/delete-node/ cpu@100; /delete-node/ cpu@100;
}; };
timer {
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
}; };

8
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@ -1097,9 +1097,9 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
}; };
}; };

7
arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
View File

@ -15,11 +15,4 @@
/delete-node/ cpu-map; /delete-node/ cpu-map;
/delete-node/ cpu@100; /delete-node/ cpu@100;
}; };
timer {
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
}; };