iommu/vt-d: Enable 5-level paging mode in the PASID entry
If the CPU has support for 5-level paging enabled and the IOMMU also supports 5-level paging then enable the 5-level paging mode for first- level translations - used when SVM is enabled. Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -26,6 +26,10 @@
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#include <linux/interrupt.h>
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#include <linux/interrupt.h>
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#include <asm/page.h>
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#include <asm/page.h>
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#define PASID_ENTRY_P BIT_ULL(0)
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#define PASID_ENTRY_FLPM_5LP BIT_ULL(9)
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#define PASID_ENTRY_SRE BIT_ULL(11)
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static irqreturn_t prq_event_thread(int irq, void *d);
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static irqreturn_t prq_event_thread(int irq, void *d);
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struct pasid_entry {
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struct pasid_entry {
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@ -300,6 +304,7 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_
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struct intel_svm_dev *sdev;
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struct intel_svm_dev *sdev;
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struct intel_svm *svm = NULL;
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struct intel_svm *svm = NULL;
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struct mm_struct *mm = NULL;
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struct mm_struct *mm = NULL;
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u64 pasid_entry_val;
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int pasid_max;
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int pasid_max;
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int ret;
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int ret;
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@ -406,9 +411,15 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_
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kfree(sdev);
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kfree(sdev);
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goto out;
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goto out;
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}
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}
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iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1;
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pasid_entry_val = (u64)__pa(mm->pgd) | PASID_ENTRY_P;
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} else
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} else
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iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11);
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pasid_entry_val = (u64)__pa(init_mm.pgd) |
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PASID_ENTRY_P | PASID_ENTRY_SRE;
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if (cpu_feature_enabled(X86_FEATURE_LA57))
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pasid_entry_val |= PASID_ENTRY_FLPM_5LP;
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iommu->pasid_table[svm->pasid].val = pasid_entry_val;
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wmb();
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wmb();
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/* In caching mode, we still have to flush with PASID 0 when
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/* In caching mode, we still have to flush with PASID 0 when
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* a PASID table entry becomes present. Not entirely clear
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* a PASID table entry becomes present. Not entirely clear
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