A few more Qualcomm Arm32 DeviceTree updates fr v6.8
The recently introduced changes to the SDX55 USB controller interrupt flags prevents the USB controller from probing. These patches corrects the PDC's interrupt-cells, so that appropriate interrupt controller (which supports both-edge interrupts) can be used instead, which resolves the issue. The SDX55 PCIe PHY base address is also adjusted, from a mistake when the node recently was transitioned to the modernized DeviceTree binding. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmWQ35oVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FDpQP/3tGAnkKGDTiN7s/K2LVS0nDwM17 lyAyp/g+k7ja9FH2uwZ+ImUVSLS9s7PhaK6H8PGF/KMF3S803UKOGY7ElNjnYWOb +MPbfQY8bKAsfGctkd2vRiVjzb0XgKep+BCs7TObO4BLkUGaYgUrU7QKZd9RR4xC 1MXvJJZS2DMjmpJX52ZLbGYHryLMMyUl3NRCyGy8oxVRgeGBAySUFsdUXQmwrvfn Smaax9rLmzEJEgqELjtlwTwHlvmQ7pDtYQ6OKkXHxXUuVdTWZbU0+7i5NTeW6YQv TFkQKSRuVPCk+rmq5mF5HJ/uXUVD537THsanIVRJL7wYoo2sWzYGwQAcMPdMlP3M +9izr6w1W/BSQEzrRyQ6otV2+FX5DnuNjJlI7e9t0nS9+qwpmkoGf4FrbS/sIEsh 1/JHUJCSvQ5ErOEZh6XuTMcbxjp4qbT+zGCFJIC4RXA9kOgPd8gEYw8M3nAhoyxo l8pVHa5SdDBdL2UzTO08QErifyEj/6n0wY0tk5nkDhQb8sCRQpXT6lnw2zvk+Lj1 ZnU06IYg6sCOGgy2rk4K2B3RT6UOr3Vn/HowYtmt9ycka2jIPKUwdM0WmSYEVbTv j72oFjdICUqwg2Eqycbj/ZjMYtFTFG1SG8d5CIZ6Ary6dHwvxWm5PxcEnsAhSOBB VFh5WkS6TEVIlJ3m =uLxU -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmWT3KsACgkQYKtH/8kJ UidbphAAn+4Nb4RzhHMh1NhLxSoIpxmyYqPb+NQb2NHbroU5VMrrkVLy7KEMojTa A+sC/+9+xrzn/PSb38t6I5go+ObpPGGGqCoH8FLJ2kzyQMIMl+xrkqQ+T7kRqxSE 1OPq6zBDKl5osdc1ROFCHN7MUz7R50guVUxQjJpMWSsBnFpepKiKv4JvEKZnrMAt nDjmymwEvdODLnCbtDdMB5czZQNLh4AtobI8iqsgGXwyoBNOQ1WY3PkRh+hTc7Ml lmccfIizelBDpbCmrvmq94lKoF2JIdNS5kLUCV54iTAo88F2KVrhDu+NRaGAZI0o ZDGDI3yf8Tn6G+epsTq/BPSm3mhjZNTLB/rfxE8ImQa/MM4aH4uEb7ekCRZarrLU FCDs2Bkkzlz34/5Zx5Ht3Pd11/erfvOWShhfpYwJZ0T+iUlWF5xxIJefe2lHXKmP 5fwdaH+t5nEZAydS/BiqatGpcV4Kz5g2eQdeb16dzs7q1vr9YY33GlKqGROVxFua fYlKu/UDjDIJa2VQdOq8NE3VN/FvyKa/4T9RQMIYJ+W7nhY4itOeoPsn5A94B+4x zR0GLoa7jJZA4cd2sM+PGCnyjdLiRR7x5u6D10j1+3QSuGYVwhByo4e/DBzhAu39 jb8AoBQHyEAHpQOIYBSnntBoks7se8GcS2i5Cq8QBmYazfhG3P4= =OFU8 -----END PGP SIGNATURE----- Merge tag 'qcom-arm32-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt A few more Qualcomm Arm32 DeviceTree updates fr v6.8 The recently introduced changes to the SDX55 USB controller interrupt flags prevents the USB controller from probing. These patches corrects the PDC's interrupt-cells, so that appropriate interrupt controller (which supports both-edge interrupts) can be used instead, which resolves the issue. The SDX55 PCIe PHY base address is also adjusted, from a mistake when the node recently was transitioned to the modernized DeviceTree binding. * tag 'qcom-arm32-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: ARM: dts: qcom: sdx55: Fix the base address of PCIe PHY ARM: dts: qcom: sdx55: fix USB SS wakeup ARM: dts: qcom: sdx55: fix USB DP/DM HS PHY interrupts ARM: dts: qcom: sdx55: fix pdc '#interrupt-cells' Link: https://lore.kernel.org/r/20231231033153.3262575-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
2f5ed2cacc
@ -431,9 +431,9 @@
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status = "disabled";
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};
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pcie_phy: phy@1c07000 {
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pcie_phy: phy@1c06000 {
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compatible = "qcom,sdx55-qmp-pcie-phy";
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reg = <0x01c07000 0x2000>;
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reg = <0x01c06000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@ -580,10 +580,10 @@
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<&gcc GCC_USB30_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <200000000>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_EDGE_BOTH>,
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<GIC_SPI 157 IRQ_TYPE_EDGE_BOTH>;
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interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 51 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 11 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 10 IRQ_TYPE_EDGE_BOTH>;
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interrupt-names = "hs_phy_irq", "ss_phy_irq",
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"dm_hs_phy_irq", "dp_hs_phy_irq";
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@ -607,7 +607,7 @@
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compatible = "qcom,sdx55-pdc", "qcom,pdc";
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reg = <0x0b210000 0x30000>;
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qcom,pdc-ranges = <0 179 52>;
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#interrupt-cells = <3>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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