x86/apic: Nuke empty init_apic_ldr() callbacks
apic::init_apic_ldr() is only invoked when the APIC is initialized. So there is really no point in having: - Default empty callbacks all over the place - Two implementations of the actual LDR init function where one is just unreadable gunk but does exactly the same as the other. Make the apic::init_apic_ldr() invocation conditional, remove the empty callbacks and consolidate the two implementation into one. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Juergen Gross <jgross@suse.com> # Xen PV (dom0 and unpriv. guest)
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@ -445,8 +445,6 @@ extern void generic_bigsmp_probe(void);
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#include <asm/smp.h>
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#define APIC_DFR_VALUE (APIC_DFR_FLAT)
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extern struct apic apic_noop;
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static inline unsigned int read_apic_id(void)
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@ -1578,8 +1578,11 @@ static void setup_local_APIC(void)
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/*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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* document number 292116).
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*
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* Except for APICs which operate in physical destination mode.
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*/
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if (apic->init_apic_ldr)
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apic->init_apic_ldr();
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/*
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@ -6,6 +6,8 @@
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#include <linux/irq.h>
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#include <asm/apic.h>
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#include "local.h"
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u32 apic_default_calc_apicid(unsigned int cpu)
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{
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return per_cpu(x86_cpu_to_apicid, cpu);
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@ -39,3 +41,17 @@ int default_apic_id_valid(u32 apicid)
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{
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return (apicid < 255);
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}
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/*
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* Set up the logical destination ID when the APIC operates in logical
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* destination mode.
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*/
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void default_init_apic_ldr(void)
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{
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unsigned long val;
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apic_write(APIC_DFR, APIC_DFR_FLAT);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
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apic_write(APIC_LDR, val);
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}
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@ -28,26 +28,6 @@ static int flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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return 1;
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}
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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void flat_init_apic_ldr(void)
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{
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unsigned long val;
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unsigned long num, id;
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num = smp_processor_id();
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id = 1UL << num;
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apic_write(APIC_DFR, APIC_DFR_FLAT);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(id);
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apic_write(APIC_LDR, val);
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}
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static void _flat_send_IPI_mask(unsigned long mask, int vector)
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{
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unsigned long flags;
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@ -119,7 +99,7 @@ static struct apic apic_flat __ro_after_init = {
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.disable_esr = 0,
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.check_apicid_used = NULL,
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.init_apic_ldr = flat_init_apic_ldr,
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.init_apic_ldr = default_init_apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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@ -175,15 +155,6 @@ static int physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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return 0;
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}
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static void physflat_init_apic_ldr(void)
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{
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/*
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* LDR and DFR are not involved in physflat mode, rather:
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* "In physical destination mode, the destination processor is
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* specified by its local APIC ID [...]." (Intel SDM, 10.6.2.1)
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*/
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}
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static int physflat_probe(void)
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{
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if (apic == &apic_physflat || num_possible_cpus() > 8 ||
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@ -207,7 +178,6 @@ static struct apic apic_physflat __ro_after_init = {
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.disable_esr = 0,
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.check_apicid_used = NULL,
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.init_apic_ldr = physflat_init_apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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@ -14,7 +14,6 @@
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#include <asm/apic.h>
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static void noop_init_apic_ldr(void) { }
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static void noop_send_IPI(int cpu, int vector) { }
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static void noop_send_IPI_mask(const struct cpumask *cpumask, int vector) { }
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static void noop_send_IPI_mask_allbutself(const struct cpumask *cpumask, int vector) { }
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@ -94,7 +93,6 @@ struct apic apic_noop __ro_after_init = {
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.disable_esr = 0,
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.check_apicid_used = default_check_apicid_used,
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.init_apic_ldr = noop_init_apic_ldr,
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.ioapic_phys_id_map = default_ioapic_phys_id_map,
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.setup_apic_routing = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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@ -252,7 +252,6 @@ static const struct apic apic_numachip1 __refconst = {
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.disable_esr = 0,
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.check_apicid_used = NULL,
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.init_apic_ldr = flat_init_apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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@ -297,7 +296,6 @@ static const struct apic apic_numachip2 __refconst = {
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.disable_esr = 0,
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.check_apicid_used = NULL,
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.init_apic_ldr = flat_init_apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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@ -28,14 +28,6 @@ static bool bigsmp_check_apicid_used(physid_mask_t *map, int apicid)
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return false;
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}
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/*
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* bigsmp enables physical destination mode
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* and doesn't use LDR and DFR
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*/
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static void bigsmp_init_apic_ldr(void)
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{
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}
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static void bigsmp_setup_apic_routing(void)
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{
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printk(KERN_INFO
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@ -108,7 +100,6 @@ static struct apic apic_bigsmp __ro_after_init = {
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.disable_esr = 1,
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.check_apicid_used = bigsmp_check_apicid_used,
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.init_apic_ldr = bigsmp_init_apic_ldr,
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.ioapic_phys_id_map = bigsmp_ioapic_phys_id_map,
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.setup_apic_routing = bigsmp_setup_apic_routing,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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@ -13,9 +13,6 @@
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#include <asm/irq_vectors.h>
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#include <asm/apic.h>
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/* APIC flat 64 */
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void flat_init_apic_ldr(void);
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/* X2APIC */
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int x2apic_apic_id_valid(u32 apicid);
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int x2apic_apic_id_registered(void);
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@ -46,6 +43,8 @@ static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector,
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return icr;
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}
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void default_init_apic_ldr(void);
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void __default_send_IPI_shortcut(unsigned int shortcut, int vector);
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/*
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@ -32,21 +32,6 @@ static int default_apic_id_registered(void)
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return physid_isset(read_apic_id(), phys_cpu_present_map);
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}
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/*
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* Set up the logical destination ID. Intel recommends to set DFR, LDR and
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* TPR before enabling an APIC. See e.g. "AP-388 82489DX User's Manual"
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* (Intel document number 292116).
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*/
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static void default_init_apic_ldr(void)
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{
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unsigned long val;
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apic_write(APIC_DFR, APIC_DFR_VALUE);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
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apic_write(APIC_LDR, val);
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}
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static int default_phys_pkg_id(int cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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@ -91,10 +91,6 @@ static void x2apic_send_IPI_all(int vector)
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__x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC);
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}
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static void init_x2apic_ldr(void)
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{
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}
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static int x2apic_phys_probe(void)
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{
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if (!x2apic_mode)
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@ -169,7 +165,6 @@ static struct apic apic_x2apic_phys __ro_after_init = {
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.disable_esr = 0,
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.check_apicid_used = NULL,
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.init_apic_ldr = init_x2apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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@ -788,10 +788,6 @@ static int uv_apic_id_registered(void)
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return 1;
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}
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static void uv_init_apic_ldr(void)
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{
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}
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static u32 apic_uv_calc_apicid(unsigned int cpu)
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{
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return apic_default_calc_apicid(cpu);
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@ -841,7 +837,6 @@ static struct apic apic_x2apic_uv_x __ro_after_init = {
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.disable_esr = 0,
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.check_apicid_used = NULL,
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.init_apic_ldr = uv_init_apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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@ -149,7 +149,6 @@ static struct apic xen_pv_apic = {
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.disable_esr = 0,
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.check_apicid_used = default_check_apicid_used, /* Used on 32-bit */
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.init_apic_ldr = xen_noop, /* setup_local_APIC calls it */
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.ioapic_phys_id_map = default_ioapic_phys_id_map, /* Used on 32-bit */
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.setup_apic_routing = NULL,
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.cpu_present_to_apicid = xen_cpu_present_to_apicid,
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