phy: qcom-qmp-pcie: merge driver data
The PCIe QMP PHY driver only manages a single PHY so merge the old qcom_qmp and qmp_phy structures and drop the PHY array. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Johan Hovold
Vinod Koul
parent
cebc6ca76e
commit
2fdedef3ea
@ -1365,56 +1365,26 @@ struct qmp_phy_cfg {
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unsigned long pipe_clock_rate;
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};
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/**
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* struct qmp_phy - per-lane phy descriptor
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*
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* @phy: generic phy
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* @cfg: phy specific configuration
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* @serdes: iomapped memory space for phy's serdes (i.e. PLL)
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* @tx: iomapped memory space for lane's tx
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* @rx: iomapped memory space for lane's rx
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* @pcs: iomapped memory space for lane's pcs
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* @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
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* @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
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* @pcs_misc: iomapped memory space for lane's pcs_misc
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* @pipe_clk: pipe clock
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* @qmp: QMP phy to which this lane belongs
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* @mode: currently selected PHY mode
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*/
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struct qmp_phy {
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struct phy *phy;
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const struct qmp_phy_cfg *cfg;
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void __iomem *serdes;
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void __iomem *tx;
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void __iomem *rx;
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void __iomem *pcs;
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void __iomem *tx2;
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void __iomem *rx2;
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void __iomem *pcs_misc;
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struct clk *pipe_clk;
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struct qcom_qmp *qmp;
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int mode;
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};
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/**
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* struct qcom_qmp - structure holding QMP phy block attributes
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*
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* @dev: device
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*
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* @clks: array of clocks required by phy
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* @resets: array of resets required by phy
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* @vregs: regulator supplies bulk data
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*
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* @phys: array of per-lane phy descriptors
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*/
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struct qcom_qmp {
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struct qmp_pcie {
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struct device *dev;
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const struct qmp_phy_cfg *cfg;
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void __iomem *serdes;
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void __iomem *pcs;
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void __iomem *pcs_misc;
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void __iomem *tx;
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void __iomem *rx;
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void __iomem *tx2;
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void __iomem *rx2;
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struct clk *pipe_clk;
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struct clk_bulk_data *clks;
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struct reset_control_bulk_data *resets;
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struct regulator_bulk_data *vregs;
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struct qmp_phy **phys;
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struct phy *phy;
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int mode;
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};
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static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
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@ -1850,9 +1820,9 @@ static void qmp_pcie_configure(void __iomem *base,
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qmp_pcie_configure_lane(base, tbl, num, 0xff);
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}
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static void qmp_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)
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static void qmp_pcie_serdes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables)
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{
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void __iomem *serdes = qphy->serdes;
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void __iomem *serdes = qmp->serdes;
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if (!tables)
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return;
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@ -1860,11 +1830,11 @@ static void qmp_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_
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qmp_pcie_configure(serdes, tables->serdes, tables->serdes_num);
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}
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static void qmp_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)
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static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables)
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{
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *tx = qphy->tx;
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void __iomem *rx = qphy->rx;
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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void __iomem *tx = qmp->tx;
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void __iomem *rx = qmp->rx;
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if (!tables)
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return;
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@ -1872,17 +1842,17 @@ static void qmp_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_t
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qmp_pcie_configure_lane(tx, tables->tx, tables->tx_num, 1);
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if (cfg->lanes >= 2)
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qmp_pcie_configure_lane(qphy->tx2, tables->tx, tables->tx_num, 2);
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qmp_pcie_configure_lane(qmp->tx2, tables->tx, tables->tx_num, 2);
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qmp_pcie_configure_lane(rx, tables->rx, tables->rx_num, 1);
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if (cfg->lanes >= 2)
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qmp_pcie_configure_lane(qphy->rx2, tables->rx, tables->rx_num, 2);
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qmp_pcie_configure_lane(qmp->rx2, tables->rx, tables->rx_num, 2);
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}
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static void qmp_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)
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static void qmp_pcie_pcs_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables)
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{
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void __iomem *pcs = qphy->pcs;
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void __iomem *pcs_misc = qphy->pcs_misc;
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void __iomem *pcs = qmp->pcs;
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void __iomem *pcs_misc = qmp->pcs_misc;
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if (!tables)
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return;
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@ -1893,9 +1863,8 @@ static void qmp_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tab
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static int qmp_pcie_init(struct phy *phy)
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{
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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struct qmp_pcie *qmp = phy_get_drvdata(phy);
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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int ret;
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ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
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@ -1932,9 +1901,8 @@ err_disable_regulators:
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static int qmp_pcie_exit(struct phy *phy)
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{
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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struct qmp_pcie *qmp = phy_get_drvdata(phy);
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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reset_control_bulk_assert(cfg->num_resets, qmp->resets);
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@ -1947,11 +1915,10 @@ static int qmp_pcie_exit(struct phy *phy)
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static int qmp_pcie_power_on(struct phy *phy)
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{
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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struct qmp_pcie *qmp = phy_get_drvdata(phy);
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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const struct qmp_phy_cfg_tables *mode_tables;
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void __iomem *pcs = qphy->pcs;
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void __iomem *pcs = qmp->pcs;
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void __iomem *status;
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unsigned int mask, val;
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int ret;
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@ -1959,26 +1926,26 @@ static int qmp_pcie_power_on(struct phy *phy)
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qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
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cfg->pwrdn_ctrl);
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if (qphy->mode == PHY_MODE_PCIE_RC)
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if (qmp->mode == PHY_MODE_PCIE_RC)
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mode_tables = cfg->tables_rc;
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else
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mode_tables = cfg->tables_ep;
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qmp_pcie_serdes_init(qphy, &cfg->tables);
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qmp_pcie_serdes_init(qphy, mode_tables);
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qmp_pcie_serdes_init(qmp, &cfg->tables);
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qmp_pcie_serdes_init(qmp, mode_tables);
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ret = clk_prepare_enable(qphy->pipe_clk);
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ret = clk_prepare_enable(qmp->pipe_clk);
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if (ret) {
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dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
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return ret;
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}
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/* Tx, Rx, and PCS configurations */
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qmp_pcie_lanes_init(qphy, &cfg->tables);
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qmp_pcie_lanes_init(qphy, mode_tables);
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qmp_pcie_lanes_init(qmp, &cfg->tables);
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qmp_pcie_lanes_init(qmp, mode_tables);
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qmp_pcie_pcs_init(qphy, &cfg->tables);
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qmp_pcie_pcs_init(qphy, mode_tables);
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qmp_pcie_pcs_init(qmp, &cfg->tables);
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qmp_pcie_pcs_init(qmp, mode_tables);
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/* Pull PHY out of reset state */
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qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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@ -2001,27 +1968,27 @@ static int qmp_pcie_power_on(struct phy *phy)
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return 0;
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err_disable_pipe_clk:
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clk_disable_unprepare(qphy->pipe_clk);
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clk_disable_unprepare(qmp->pipe_clk);
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return ret;
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}
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static int qmp_pcie_power_off(struct phy *phy)
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{
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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struct qmp_pcie *qmp = phy_get_drvdata(phy);
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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clk_disable_unprepare(qphy->pipe_clk);
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clk_disable_unprepare(qmp->pipe_clk);
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/* PHY reset */
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qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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/* stop SerDes and Phy-Coding-Sublayer */
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qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL],
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qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
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SERDES_START | PCS_START);
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/* Put PHY into POWER DOWN state: active low */
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qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
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qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
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cfg->pwrdn_ctrl);
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return 0;
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@ -2055,12 +2022,12 @@ static int qmp_pcie_disable(struct phy *phy)
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static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode)
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{
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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struct qmp_pcie *qmp = phy_get_drvdata(phy);
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switch (submode) {
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case PHY_MODE_PCIE_RC:
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case PHY_MODE_PCIE_EP:
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qphy->mode = submode;
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qmp->mode = submode;
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break;
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default:
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dev_err(&phy->dev, "Unsupported submode %d\n", submode);
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@ -2072,7 +2039,7 @@ static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode)
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static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
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{
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struct qcom_qmp *qmp = dev_get_drvdata(dev);
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struct qmp_pcie *qmp = dev_get_drvdata(dev);
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int num = cfg->num_vregs;
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int i;
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@ -2088,7 +2055,7 @@ static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
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static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
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{
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struct qcom_qmp *qmp = dev_get_drvdata(dev);
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struct qmp_pcie *qmp = dev_get_drvdata(dev);
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int i;
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int ret;
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@ -2109,7 +2076,7 @@ static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg
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static int qmp_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
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{
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struct qcom_qmp *qmp = dev_get_drvdata(dev);
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struct qmp_pcie *qmp = dev_get_drvdata(dev);
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int num = cfg->num_clks;
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int i;
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@ -2146,7 +2113,7 @@ static void phy_clk_release_provider(void *res)
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* clk | +-------+ | +-----+
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* +---------------+
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*/
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static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
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static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)
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{
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struct clk_fixed_rate *fixed;
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struct clk_init_data init = { };
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@ -2168,8 +2135,8 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
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* Controllers using QMP PHY-s use 125MHz pipe clock interface
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* unless other frequency is specified in the PHY config.
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*/
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if (qmp->phys[0]->cfg->pipe_clock_rate)
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fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate;
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if (qmp->cfg->pipe_clock_rate)
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fixed->fixed_rate = qmp->cfg->pipe_clock_rate;
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else
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fixed->fixed_rate = 125000000;
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@ -2197,97 +2164,92 @@ static const struct phy_ops qmp_pcie_ops = {
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.owner = THIS_MODULE,
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};
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static int qmp_pcie_create(struct device *dev, struct device_node *np, int id,
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static int qmp_pcie_create(struct device *dev, struct device_node *np,
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void __iomem *serdes, const struct qmp_phy_cfg *cfg)
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{
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struct qcom_qmp *qmp = dev_get_drvdata(dev);
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struct qmp_pcie *qmp = dev_get_drvdata(dev);
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struct phy *generic_phy;
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struct qmp_phy *qphy;
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int ret;
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qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
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if (!qphy)
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return -ENOMEM;
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qmp->mode = PHY_MODE_PCIE_RC;
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qphy->mode = PHY_MODE_PCIE_RC;
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qmp->cfg = cfg;
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qmp->serdes = serdes;
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qphy->cfg = cfg;
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qphy->serdes = serdes;
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/*
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* Get memory resources for the PHY:
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* Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
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* For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
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* For single lane PHYs: pcs_misc (optional) -> 3.
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*/
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qphy->tx = devm_of_iomap(dev, np, 0, NULL);
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if (IS_ERR(qphy->tx))
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return PTR_ERR(qphy->tx);
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qmp->tx = devm_of_iomap(dev, np, 0, NULL);
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if (IS_ERR(qmp->tx))
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return PTR_ERR(qmp->tx);
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if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy"))
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qphy->rx = qphy->tx;
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qmp->rx = qmp->tx;
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else
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qphy->rx = devm_of_iomap(dev, np, 1, NULL);
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if (IS_ERR(qphy->rx))
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return PTR_ERR(qphy->rx);
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qmp->rx = devm_of_iomap(dev, np, 1, NULL);
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if (IS_ERR(qmp->rx))
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return PTR_ERR(qmp->rx);
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qphy->pcs = devm_of_iomap(dev, np, 2, NULL);
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if (IS_ERR(qphy->pcs))
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return PTR_ERR(qphy->pcs);
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qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
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if (IS_ERR(qmp->pcs))
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return PTR_ERR(qmp->pcs);
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if (cfg->lanes >= 2) {
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qphy->tx2 = devm_of_iomap(dev, np, 3, NULL);
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if (IS_ERR(qphy->tx2))
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return PTR_ERR(qphy->tx2);
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qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
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if (IS_ERR(qmp->tx2))
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return PTR_ERR(qmp->tx2);
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qphy->rx2 = devm_of_iomap(dev, np, 4, NULL);
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if (IS_ERR(qphy->rx2))
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return PTR_ERR(qphy->rx2);
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qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
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if (IS_ERR(qmp->rx2))
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return PTR_ERR(qmp->rx2);
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qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
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qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
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} else {
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qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
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qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
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}
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if (IS_ERR(qphy->pcs_misc) &&
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if (IS_ERR(qmp->pcs_misc) &&
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of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
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qphy->pcs_misc = qphy->pcs + 0x400;
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qmp->pcs_misc = qmp->pcs + 0x400;
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if (IS_ERR(qphy->pcs_misc)) {
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if (IS_ERR(qmp->pcs_misc)) {
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if (cfg->tables.pcs_misc ||
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(cfg->tables_rc && cfg->tables_rc->pcs_misc) ||
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(cfg->tables_ep && cfg->tables_ep->pcs_misc))
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return PTR_ERR(qphy->pcs_misc);
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(cfg->tables_ep && cfg->tables_ep->pcs_misc)) {
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return PTR_ERR(qmp->pcs_misc);
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}
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}
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||||
qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
|
||||
if (IS_ERR(qphy->pipe_clk)) {
|
||||
return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
|
||||
"failed to get lane%d pipe clock\n", id);
|
||||
qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
|
||||
if (IS_ERR(qmp->pipe_clk)) {
|
||||
return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
|
||||
"failed to get pipe clock\n");
|
||||
}
|
||||
|
||||
generic_phy = devm_phy_create(dev, np, &qmp_pcie_ops);
|
||||
if (IS_ERR(generic_phy)) {
|
||||
ret = PTR_ERR(generic_phy);
|
||||
dev_err(dev, "failed to create qphy %d\n", ret);
|
||||
dev_err(dev, "failed to create PHY: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
qphy->phy = generic_phy;
|
||||
qphy->qmp = qmp;
|
||||
qmp->phys[id] = qphy;
|
||||
phy_set_drvdata(generic_phy, qphy);
|
||||
qmp->phy = generic_phy;
|
||||
phy_set_drvdata(generic_phy, qmp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qmp_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct qcom_qmp *qmp;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *child;
|
||||
struct phy_provider *phy_provider;
|
||||
void __iomem *serdes;
|
||||
const struct qmp_phy_cfg *cfg = NULL;
|
||||
struct qmp_pcie *qmp;
|
||||
int num, id;
|
||||
int ret;
|
||||
|
||||
@ -2326,14 +2288,10 @@ static int qmp_pcie_probe(struct platform_device *pdev)
|
||||
if (num > 1)
|
||||
return -EINVAL;
|
||||
|
||||
qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
|
||||
if (!qmp->phys)
|
||||
return -ENOMEM;
|
||||
|
||||
id = 0;
|
||||
for_each_available_child_of_node(dev->of_node, child) {
|
||||
/* Create per-lane phy */
|
||||
ret = qmp_pcie_create(dev, child, id, serdes, cfg);
|
||||
ret = qmp_pcie_create(dev, child, serdes, cfg);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to create lane%d phy, %d\n",
|
||||
id, ret);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user