ARM: entry: no need to reload the SPSR value from struct pt_regs
The SVC IRQ, prefetch and data abort handlers preserve the SPSR value via r5 across the exception. Rather than re-loading it from pt_regs, use the preserved value instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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40f0b90a2f
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@ -195,10 +195,6 @@ __dabt_svc:
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@
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@
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disable_irq_notrace
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disable_irq_notrace
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@
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@ restore SPSR and restart the instruction
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@
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ldr r5, [sp, #S_PSR]
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#ifdef CONFIG_TRACE_IRQFLAGS
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#ifdef CONFIG_TRACE_IRQFLAGS
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tst r5, #PSR_I_BIT
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tst r5, #PSR_I_BIT
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bleq trace_hardirqs_on
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bleq trace_hardirqs_on
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@ -223,7 +219,7 @@ __irq_svc:
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tst r0, #_TIF_NEED_RESCHED
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tst r0, #_TIF_NEED_RESCHED
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blne svc_preempt
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blne svc_preempt
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#endif
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#endif
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ldr r5, [sp, #S_PSR]
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#ifdef CONFIG_TRACE_IRQFLAGS
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#ifdef CONFIG_TRACE_IRQFLAGS
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@ The parent context IRQs must have been enabled to get here in
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@ The parent context IRQs must have been enabled to get here in
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@ the first place, so there's no point checking the PSR I bit.
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@ the first place, so there's no point checking the PSR I bit.
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@ -308,10 +304,6 @@ __pabt_svc:
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@
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@
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disable_irq_notrace
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disable_irq_notrace
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@
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@ restore SPSR and restart the instruction
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@
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ldr r5, [sp, #S_PSR]
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#ifdef CONFIG_TRACE_IRQFLAGS
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#ifdef CONFIG_TRACE_IRQFLAGS
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tst r5, #PSR_I_BIT
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tst r5, #PSR_I_BIT
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bleq trace_hardirqs_on
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bleq trace_hardirqs_on
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