Actions Semi ARM64 based SoC DT for 4.13
This adds an initial DT for the S900 SoC and a devboard based on it. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJZTULJAAoJEPou0S0+fgE/00gP/3V47/jMZmIcRZymiRXUkZAc cZiIkeKXa0LEXQPk5iTAVXCU7vfhWHHq3g9lA+CWMhbBKO+6K/RwipdscqAxLNfF kaIIO4M1CEVB9R55JR2jTd6qEHBD+MibTxYc2bbfrWJtbaQJWZ+ep0oKqpOccoby BRb5yhBt0b0K4GOlgOQHNVIc6sbdhH8ZJ+n/Dqj57eDxzH/u+DUaWdwAIHDaN8Qw +qAM4HTYSXnlwjWgRgeBws7adDV8wDLbQwpNrmHjDBGxZ8BTIZxrnydKG7AUMIPi o8A50c7khq4xFQN+IhhNrhwQpilMRjlZc84DwqBsFdaUzei4jYZmY8udxKyuJdhr ZMerSnvoBOew/KpyvhxaT0aHD0Zlxzl6yKy7dw3FAbqnQTUUmpwp2kM1bsNteMwU FD5YvLv04R8y9w8XJdsPATQiqu06dZIBZdHubI4D3hWMMYi963eH7KE9ON8mq5Uc d7Ex1+q9DvjiwOlPtTAcLoeAQeVKeojrDQTTpH4GR3PtukJVBLzS1IiFl1qweele G1i0WTUgSuYmlvoWOIX4jzeejiXab5WOUszdsIT5qx0LIZKnS/XfQe/kjOYcto6Z 3244hW7AXkdVGOieUX4d+DiizlvJe6VPbq5RJ6Ka5ZmWIdUbH5KkDT4F/jSoi4d4 Ny4hC2twmGfmUIFqbBpp =WMGS -----END PGP SIGNATURE----- Merge tag 'actions-arm64-dt-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/dt64 Pull "Actions Semi ARM64 based SoC DT for 4.13" from Andreas Färber: This adds an initial DT for the S900 SoC and a devboard based on it. * tag 'actions-arm64-dt-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions: arm64: dts: Add Actions Semi S900 and Bubblegum-96 dt-bindings: Add vendor prefix for uCRobotics
This commit is contained in:
Arnd Bergmann
commit
30c2a65828
@ -333,6 +333,7 @@ tronfy Tronfy
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tronsmart Tronsmart
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truly Truly Semiconductors Limited
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tyan Tyan Computer Corporation
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ucrobotics uCRobotics
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udoo Udoo
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uniwest United Western Technologies Corp (UniWest)
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upisemi uPI Semiconductor Corp.
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@ -1,3 +1,4 @@
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dts-dirs += actions
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dts-dirs += al
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dts-dirs += allwinner
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dts-dirs += altera
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5
arch/arm64/boot/dts/actions/Makefile
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5
arch/arm64/boot/dts/actions/Makefile
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@ -0,0 +1,5 @@
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dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb
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35
arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
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35
arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
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@ -0,0 +1,35 @@
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/*
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* Copyright (c) 2017 Andreas Färber
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/dts-v1/;
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#include "s900.dtsi"
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/ {
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compatible = "ucrobotics,bubblegum-96", "actions,s900";
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model = "Bubblegum-96";
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aliases {
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serial5 = &uart5;
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};
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chosen {
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stdout-path = "serial5:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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};
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&timer {
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clocks = <&hosc>;
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};
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&uart5 {
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status = "okay";
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};
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164
arch/arm64/boot/dts/actions/s900.dtsi
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164
arch/arm64/boot/dts/actions/s900.dtsi
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@ -0,0 +1,164 @@
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/*
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* Copyright (c) 2017 Andreas Färber
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "actions,s900";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secmon@1f000000 {
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reg = <0x0 0x1f000000 0x0 0x1000000>;
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no-map;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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hosc: hosc {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@e00f1000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xe00f1000 0x0 0x1000>,
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<0x0 0xe00f2000 0x0 0x2000>,
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<0x0 0xe00f4000 0x0 0x2000>,
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<0x0 0xe00f6000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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uart0: serial@e0120000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0120000 0x0 0x2000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart1: serial@e0122000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0122000 0x0 0x2000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart2: serial@e0124000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0124000 0x0 0x2000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart3: serial@e0126000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0126000 0x0 0x2000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart4: serial@e0128000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0128000 0x0 0x2000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart5: serial@e012a000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe012a000 0x0 0x2000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart6: serial@e012c000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe012c000 0x0 0x2000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer: timer@e0228000 {
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compatible = "actions,s900-timer";
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reg = <0x0 0xe0228000 0x0 0x8000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "timer1";
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};
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};
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};
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