ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs
Initial support for the MStar/Sigmastar Armv7 based IP camera and dashcam SoCs. These chips are interesting in that they contain a Cortex-A7, peripherals and system memory in a single tiny QFN package that can be hand soldered allowing almost anyone to embed Linux in their projects. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Daniel Palmer
Arnd Bergmann
parent
343e8f7286
commit
312b62b661
@ -2140,6 +2140,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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W: http://linux-chenxing.org/
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F: Documentation/devicetree/bindings/arm/mstar.yaml
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F: arch/arm/mach-mstar/
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ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT
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M: Michael Petchkovsky <mkpetch@internode.on.net>
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@ -668,6 +668,8 @@ source "arch/arm/mach-mmp/Kconfig"
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source "arch/arm/mach-moxart/Kconfig"
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source "arch/arm/mach-mstar/Kconfig"
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source "arch/arm/mach-mv78xx0/Kconfig"
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source "arch/arm/mach-mvebu/Kconfig"
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@ -197,6 +197,7 @@ machine-$(CONFIG_ARCH_MXC) += imx
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machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
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machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut
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machine-$(CONFIG_ARCH_MXS) += mxs
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machine-$(CONFIG_ARCH_MSTARV7) += mstar
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machine-$(CONFIG_ARCH_NOMADIK) += nomadik
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machine-$(CONFIG_ARCH_NPCM) += npcm
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machine-$(CONFIG_ARCH_NSPIRE) += nspire
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26
arch/arm/mach-mstar/Kconfig
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26
arch/arm/mach-mstar/Kconfig
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@ -0,0 +1,26 @@
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menuconfig ARCH_MSTARV7
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bool "MStar/Sigmastar Armv7 SoC Support"
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depends on ARCH_MULTI_V7
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select ARM_GIC
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select ARM_HEAVY_MB
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help
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Support for newer MStar/Sigmastar SoC families that are
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based on Armv7 cores like the Cortex A7 and share the same
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basic hardware like the infinity and mercury series.
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if ARCH_MSTARV7
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config MACH_INFINITY
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bool "MStar/Sigmastar infinity SoC support"
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default ARCH_MSTARV7
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help
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Support for MStar/Sigmastar infinity IP camera SoCs.
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config MACH_MERCURY
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bool "MStar/Sigmastar mercury SoC support"
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default ARCH_MSTARV7
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help
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Support for MStar/Sigmastar mercury dash camera SoCs.
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Note that older Mercury2 SoCs are ARM9 based and not supported.
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endif
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1
arch/arm/mach-mstar/Makefile
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1
arch/arm/mach-mstar/Makefile
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@ -0,0 +1 @@
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obj-$(CONFIG_ARCH_MSTARV7) += mstarv7.o
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80
arch/arm/mach-mstar/mstarv7.c
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80
arch/arm/mach-mstar/mstarv7.c
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@ -0,0 +1,80 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree support for MStar/Sigmastar Armv7 SoCs
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*
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* Copyright (c) 2020 thingy.jp
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* Author: Daniel Palmer <daniel@thingy.jp>
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*/
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#include <linux/init.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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/*
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* In the u-boot code the area these registers are in is
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* called "L3 bridge" and there are register descriptions
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* for something in the same area called "AXI".
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*
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* It's not exactly known what this is but the vendor code
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* for both u-boot and linux share calls to "flush the miu pipe".
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* This seems to be to force pending CPU writes to memory so that
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* the state is right before DMA capable devices try to read
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* descriptors and data the CPU has prepared. Without doing this
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* ethernet doesn't work reliably for example.
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*/
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#define MSTARV7_L3BRIDGE_FLUSH 0x14
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#define MSTARV7_L3BRIDGE_STATUS 0x40
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#define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0)
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#define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12)
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static void __iomem *l3bridge;
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static const char * const mstarv7_board_dt_compat[] __initconst = {
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"mstar,infinity",
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"mstar,infinity3",
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"mstar,mercury5",
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NULL,
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};
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/*
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* This may need locking to deal with situations where an interrupt
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* happens while we are in here and mb() gets called by the interrupt handler.
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*
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* The vendor code did have a spin lock but it doesn't seem to be needed and
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* removing it hasn't caused any side effects so far.
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*
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* [writel|readl]_relaxed have to be used here because otherwise
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* we'd end up right back in here.
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*/
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static void mstarv7_mb(void)
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{
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/* toggle the flush miu pipe fire bit */
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writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH);
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writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge
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+ MSTARV7_L3BRIDGE_FLUSH);
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while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS)
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& MSTARV7_L3BRIDGE_STATUS_DONE)) {
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/* wait for flush to complete */
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}
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}
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static void __init mstarv7_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge");
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l3bridge = of_iomap(np, 0);
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if (l3bridge)
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soc_mb = mstarv7_mb;
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else
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pr_warn("Failed to install memory barrier, DMA will be broken!\n");
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}
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DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
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.dt_compat = mstarv7_board_dt_compat,
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.init_machine = mstarv7_init,
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MACHINE_END
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