x86: unify power/cpu_(32|64) regarding restoring processor state
In this step we do unify cpu_32.c and cpu_64.c functions that work on restoring the saved processor state. Also, we do eliminate the forward declaration of fix_processor_context() for X86_64, as it's not needed anymore. Signed-off-by: Sergio Luis <sergio@larces.uece.br> Signed-off-by: Lauro Salmito <laurosalmito@gmail.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This commit is contained in:
Sergio Luis
Rafael J. Wysocki
parent
f9ebbe53e7
commit
3134d04b77
@ -27,8 +27,6 @@ unsigned long saved_context_esi, saved_context_edi;
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unsigned long saved_context_eflags;
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#else
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/* CONFIG_X86_64 */
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static void fix_processor_context(void);
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struct saved_context saved_context;
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#endif
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@ -136,6 +134,11 @@ static void fix_processor_context(void)
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* similar stupidity.
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*/
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#ifdef CONFIG_X86_64
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get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
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syscall_init(); /* This sets MSR_*STAR and related */
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#endif
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load_TR_desc(); /* This does ltr */
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load_LDT(¤t->active_mm->context); /* This does lldt */
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@ -143,6 +146,7 @@ static void fix_processor_context(void)
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* Now maybe reload the debug registers
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*/
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if (current->thread.debugreg7) {
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#ifdef CONFIG_X86_32
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set_debugreg(current->thread.debugreg0, 0);
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set_debugreg(current->thread.debugreg1, 1);
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set_debugreg(current->thread.debugreg2, 2);
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@ -150,18 +154,40 @@ static void fix_processor_context(void)
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/* no 4 and 5 */
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set_debugreg(current->thread.debugreg6, 6);
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set_debugreg(current->thread.debugreg7, 7);
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#else
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/* CONFIG_X86_64 */
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loaddebug(¤t->thread, 0);
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loaddebug(¤t->thread, 1);
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loaddebug(¤t->thread, 2);
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loaddebug(¤t->thread, 3);
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/* no 4 and 5 */
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loaddebug(¤t->thread, 6);
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loaddebug(¤t->thread, 7);
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#endif
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}
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}
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/**
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* __restore_processor_state - restore the contents of CPU registers saved
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* by __save_processor_state()
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* @ctxt - structure to load the registers contents from
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*/
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static void __restore_processor_state(struct saved_context *ctxt)
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{
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/*
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* control registers
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*/
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/* cr4 was introduced in the Pentium CPU */
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#ifdef CONFIG_X86_32
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if (ctxt->cr4)
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write_cr4(ctxt->cr4);
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#else
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/* CONFIG X86_64 */
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wrmsrl(MSR_EFER, ctxt->efer);
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write_cr8(ctxt->cr8);
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write_cr4(ctxt->cr4);
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#endif
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write_cr3(ctxt->cr3);
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write_cr2(ctxt->cr2);
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write_cr0(ctxt->cr0);
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@ -170,12 +196,19 @@ static void __restore_processor_state(struct saved_context *ctxt)
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* now restore the descriptor tables to their proper values
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* ltr is done i fix_processor_context().
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*/
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#ifdef CONFIG_X86_32
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load_gdt(&ctxt->gdt);
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load_idt(&ctxt->idt);
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#else
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/* CONFIG_X86_64 */
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load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
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load_idt((const struct desc_ptr *)&ctxt->idt_limit);
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#endif
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/*
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* segment registers
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*/
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#ifdef CONFIG_X86_32
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loadsegment(es, ctxt->es);
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loadsegment(fs, ctxt->fs);
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loadsegment(gs, ctxt->gs);
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@ -186,6 +219,18 @@ static void __restore_processor_state(struct saved_context *ctxt)
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*/
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if (boot_cpu_has(X86_FEATURE_SEP))
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enable_sep_cpu();
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#else
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/* CONFIG_X86_64 */
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asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
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asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
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asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
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load_gs_index(ctxt->gs);
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asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
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wrmsrl(MSR_FS_BASE, ctxt->fs_base);
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wrmsrl(MSR_GS_BASE, ctxt->gs_base);
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wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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#endif
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/*
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* restore XCR0 for xsave capable cpu's.
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@ -194,9 +239,13 @@ static void __restore_processor_state(struct saved_context *ctxt)
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xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
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fix_processor_context();
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do_fpu_end();
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mtrr_ap_init();
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#ifdef CONFIG_X86_32
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mcheck_init(&boot_cpu_data);
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#endif
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}
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/* Needed by apm.c */
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@ -204,4 +253,6 @@ void restore_processor_state(void)
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{
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__restore_processor_state(&saved_context);
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}
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#ifdef CONFIG_X86_32
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EXPORT_SYMBOL(restore_processor_state);
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#endif
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@ -28,8 +28,6 @@ unsigned long saved_context_esi, saved_context_edi;
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unsigned long saved_context_eflags;
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#else
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/* CONFIG_X86_64 */
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static void fix_processor_context(void);
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struct saved_context saved_context;
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#endif
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@ -120,11 +118,57 @@ EXPORT_SYMBOL(save_processor_state);
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static void do_fpu_end(void)
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{
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/*
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* Restore FPU regs if necessary
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* Restore FPU regs if necessary.
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*/
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kernel_fpu_end();
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}
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static void fix_processor_context(void)
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{
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int cpu = smp_processor_id();
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struct tss_struct *t = &per_cpu(init_tss, cpu);
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set_tss_desc(cpu, t); /*
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* This just modifies memory; should not be
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* necessary. But... This is necessary, because
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* 386 hardware has concept of busy TSS or some
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* similar stupidity.
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*/
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#ifdef CONFIG_X86_64
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get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
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syscall_init(); /* This sets MSR_*STAR and related */
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#endif
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load_TR_desc(); /* This does ltr */
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load_LDT(¤t->active_mm->context); /* This does lldt */
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/*
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* Now maybe reload the debug registers
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*/
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if (current->thread.debugreg7) {
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#ifdef CONFIG_X86_32
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set_debugreg(current->thread.debugreg0, 0);
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set_debugreg(current->thread.debugreg1, 1);
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set_debugreg(current->thread.debugreg2, 2);
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set_debugreg(current->thread.debugreg3, 3);
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/* no 4 and 5 */
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set_debugreg(current->thread.debugreg6, 6);
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set_debugreg(current->thread.debugreg7, 7);
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#else
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/* CONFIG_X86_64 */
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loaddebug(¤t->thread, 0);
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loaddebug(¤t->thread, 1);
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loaddebug(¤t->thread, 2);
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loaddebug(¤t->thread, 3);
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/* no 4 and 5 */
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loaddebug(¤t->thread, 6);
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loaddebug(¤t->thread, 7);
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#endif
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}
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}
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/**
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* __restore_processor_state - restore the contents of CPU registers saved
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* by __save_processor_state()
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@ -135,9 +179,16 @@ static void __restore_processor_state(struct saved_context *ctxt)
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/*
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* control registers
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*/
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/* cr4 was introduced in the Pentium CPU */
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#ifdef CONFIG_X86_32
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if (ctxt->cr4)
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write_cr4(ctxt->cr4);
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#else
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/* CONFIG X86_64 */
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wrmsrl(MSR_EFER, ctxt->efer);
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write_cr8(ctxt->cr8);
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write_cr4(ctxt->cr4);
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#endif
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write_cr3(ctxt->cr3);
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write_cr2(ctxt->cr2);
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write_cr0(ctxt->cr0);
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@ -146,13 +197,31 @@ static void __restore_processor_state(struct saved_context *ctxt)
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* now restore the descriptor tables to their proper values
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* ltr is done i fix_processor_context().
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*/
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#ifdef CONFIG_X86_32
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load_gdt(&ctxt->gdt);
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load_idt(&ctxt->idt);
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#else
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/* CONFIG_X86_64 */
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load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
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load_idt((const struct desc_ptr *)&ctxt->idt_limit);
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#endif
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/*
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* segment registers
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*/
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#ifdef CONFIG_X86_32
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loadsegment(es, ctxt->es);
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loadsegment(fs, ctxt->fs);
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loadsegment(gs, ctxt->gs);
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loadsegment(ss, ctxt->ss);
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/*
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* sysenter MSRs
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*/
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if (boot_cpu_has(X86_FEATURE_SEP))
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enable_sep_cpu();
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#else
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/* CONFIG_X86_64 */
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asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
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asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
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asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
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@ -162,6 +231,7 @@ static void __restore_processor_state(struct saved_context *ctxt)
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wrmsrl(MSR_FS_BASE, ctxt->fs_base);
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wrmsrl(MSR_GS_BASE, ctxt->gs_base);
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wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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#endif
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/*
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* restore XCR0 for xsave capable cpu's.
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@ -173,41 +243,17 @@ static void __restore_processor_state(struct saved_context *ctxt)
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do_fpu_end();
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mtrr_ap_init();
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#ifdef CONFIG_X86_32
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mcheck_init(&boot_cpu_data);
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#endif
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}
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/* Needed by apm.c */
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void restore_processor_state(void)
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{
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__restore_processor_state(&saved_context);
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}
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static void fix_processor_context(void)
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{
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int cpu = smp_processor_id();
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struct tss_struct *t = &per_cpu(init_tss, cpu);
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/*
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* This just modifies memory; should not be necessary. But... This
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* is necessary, because 386 hardware has concept of busy TSS or some
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* similar stupidity.
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*/
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set_tss_desc(cpu, t);
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get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
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syscall_init(); /* This sets MSR_*STAR and related */
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load_TR_desc(); /* This does ltr */
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load_LDT(¤t->active_mm->context); /* This does lldt */
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/*
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* Now maybe reload the debug registers
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*/
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if (current->thread.debugreg7){
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loaddebug(¤t->thread, 0);
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loaddebug(¤t->thread, 1);
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loaddebug(¤t->thread, 2);
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loaddebug(¤t->thread, 3);
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/* no 4 and 5 */
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loaddebug(¤t->thread, 6);
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loaddebug(¤t->thread, 7);
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}
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}
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#ifdef CONFIG_X86_32
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EXPORT_SYMBOL(restore_processor_state);
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#endif
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