clk/samsung updates for 5.1
Exynos5433 clock driver update adding support for selected clocks of the IMEM CMU required for the cryptographic subsystem (SlimSS). -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJcWWjgAAoJEE1bIKeAnHqLcswP/iSIyEJmEgbxZDCuPya42DAZ p8tQbIFLRg0FZn1kxEMkjS07Y55EWeMxsQwwmr1FGI5H+r2M1Jz+JbUYFZBE17uz 2B9OpOZfUkIqqs3QgAwZY/Yw6gDxUKFsdusvAbuvnnHlgNdwykJIfALLMUFLYcJd 4ZQotPNYsLspy1g9nPWAZkjpyWi4UD/mHUYKMSmp9YTwwyI1rQ+Atns8ANaHEh1q CxKflOI+/VF3Xm1uMyhP1HundLavKhZHFStjD24QsM86Bycfs5652aCdZ0PHO1QV PMRkfYTMRmvkaea3ucUsm6puoobL5fadZyt9mRsJ0BkQYtNx3Aan+7dC8CMKp9gb U3QEDeuyqRPJ0IRF/xmSGi4V+ZVIZFx9U5ASC/6MUEeQaKwda00BznZbZsqYNv18 i1gQvftKfZzQyTfEgw7cSIxvGA2MqG/FZDjMGRtBtniOaEtyhVdJDxClp5R+7GZ9 ONht8q5e/bhCTbdLuLRA96aPlb2qvlcRx38L44pbv4t8raTpDx5tPBRxVd6xFYWt 3OnPGgrqRTnpx4eIKv0Pn8h19H9xQk1djOBLDjYsn+l+s+hx/DxJxnOPm9hOkSST uZt7/lTQjM/YlQrdSFR+WX5pU088MYvcB9bA1WilENoqwloTRN6iObS3mTN13VKc Z6SKxb71w5q/ZXF0aLeI =rtY5 -----END PGP SIGNATURE----- Merge tag 'clk-v5.1-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung Pull Samsung clk driver updates from Sylwester Nawrocki: Exynos5433 clock driver update adding support for selected clocks of the IMEM CMU required for the cryptographic subsystem (SlimSS). * tag 'clk-v5.1-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: exynos5433: Add selected IMEM clocks clk: samsung: dt-bindings: Document Exynos5433 IMEM CMU clk: samsung: exynos5433: Fix name typo in sssx clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocks clk: samsung: dt-bindings: Add Exynos5433 IMEM CMU clock IDs
This commit is contained in:
Stephen Boyd
commit
3144bedfca
@ -50,6 +50,8 @@ Required Properties:
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IPs.
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- "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
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which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
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- "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM
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which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
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- reg: physical base address of the controller and length of memory mapped
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region.
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@ -168,6 +170,12 @@ Required Properties:
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- aclk_cam1_400
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- aclk_cam1_552
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Input clocks for imem clock controller:
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- oscclk
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- aclk_imem_sssx_266
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- aclk_imem_266
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- aclk_imem_200
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Optional properties:
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- power-domains: a phandle to respective power domain node as described by
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generic PM domain bindings (see power/power_domain.txt for more
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@ -469,6 +477,21 @@ Example 2: Examples of clock controller nodes are listed below.
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power-domains = <&pd_cam1>;
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};
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cmu_imem: clock-controller@11060000 {
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compatible = "samsung,exynos5433-cmu-imem";
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reg = <0x11060000 0x1000>;
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#clock-cells = <1>;
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clock-names = "oscclk",
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"aclk_imem_sssx_266",
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"aclk_imem_266",
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"aclk_imem_200";
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clocks = <&xxti>,
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<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
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<&cmu_top CLK_DIV_ACLK_IMEM_266>,
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<&cmu_top CLK_DIV_ACLK_IMEM_200>;
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};
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Example 3: UART controller node that consumes the clock generated by the clock
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controller.
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@ -559,7 +559,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
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/* ENABLE_ACLK_TOP */
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GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
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ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
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GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
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GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266",
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"div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
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29, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
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@ -568,10 +568,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
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GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
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ENABLE_ACLK_TOP, 25,
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CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
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GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200",
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ENABLE_ACLK_TOP, 24,
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CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
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GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266",
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ENABLE_ACLK_TOP, 23,
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
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@ -5467,6 +5467,35 @@ static const struct samsung_cmu_info cam1_cmu_info __initconst = {
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.clk_name = "aclk_cam1_400",
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};
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/*
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* Register offset definitions for CMU_IMEM
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*/
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#define ENABLE_ACLK_IMEM_SLIMSSS 0x080c
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#define ENABLE_PCLK_IMEM_SLIMSSS 0x0908
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static const unsigned long imem_clk_regs[] __initconst = {
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ENABLE_ACLK_IMEM_SLIMSSS,
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ENABLE_PCLK_IMEM_SLIMSSS,
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};
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static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
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/* ENABLE_ACLK_IMEM_SLIMSSS */
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GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266",
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ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_PCLK_IMEM_SLIMSSS */
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GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200",
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ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
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};
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static const struct samsung_cmu_info imem_cmu_info __initconst = {
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.gate_clks = imem_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
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.nr_clk_ids = IMEM_NR_CLK,
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.clk_regs = imem_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
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.clk_name = "aclk_imem_200",
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};
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struct exynos5433_cmu_data {
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struct samsung_clk_reg_dump *clk_save;
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@ -5654,6 +5683,9 @@ static const struct of_device_id exynos5433_cmu_of_match[] = {
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}, {
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.compatible = "samsung,exynos5433-cmu-mscl",
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.data = &mscl_cmu_info,
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}, {
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.compatible = "samsung,exynos5433-cmu-imem",
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.data = &imem_cmu_info,
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}, {
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},
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};
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@ -156,7 +156,7 @@
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#define CLK_ACLK_G2D_266 220
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#define CLK_ACLK_G2D_400 221
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#define CLK_ACLK_G3D_400 222
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#define CLK_ACLK_IMEM_SSX_266 223
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#define CLK_ACLK_IMEM_SSSX_266 223
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#define CLK_ACLK_BUS0_400 224
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#define CLK_ACLK_BUS1_400 225
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#define CLK_ACLK_IMEM_200 226
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@ -1406,4 +1406,10 @@
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#define CAM1_NR_CLK 113
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/* CMU_IMEM */
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#define CLK_ACLK_SLIMSSS 2
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#define CLK_PCLK_SLIMSSS 35
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#define IMEM_NR_CLK 36
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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