Merge branch 'pci/enumeration'
- add decoding for 16 GT/s link speed (Jay Fang) - add interfaces to get max link speed and width (Tal Gilboa) - add pcie_bandwidth_capable() to compute max supported link bandwidth (Tal Gilboa) - add pcie_bandwidth_available() to compute bandwidth available to device (Tal Gilboa) - add pcie_print_link_status() to log link speed and whether it's limited (Tal Gilboa) - use PCI core interfaces to report when device performance may be limited by its slot instead of doing it in each driver (Tal Gilboa) * pci/enumeration: fm10k: Report PCIe link properties with pcie_print_link_status() net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth net/mlx5: Report PCIe link properties with pcie_print_link_status() net/mlx4_core: Report PCIe link properties with pcie_print_link_status() PCI: Add pcie_print_link_status() to log link speed and whether it's limited PCI: Add pcie_bandwidth_available() to compute bandwidth available to device PCI: Add pcie_bandwidth_capable() to compute max supported link bandwidth PCI: Add pcie_get_width_cap() to find max supported link width PCI: Add pcie_get_speed_cap() to find max supported link speed PCI: Add decoding for 16 GT/s link speed
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@ -256,6 +256,7 @@ enum pci_bus_speed {
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PCIE_SPEED_2_5GT = 0x14,
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PCIE_SPEED_5_0GT = 0x15,
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PCIE_SPEED_8_0GT = 0x16,
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PCIE_SPEED_16_0GT = 0x17,
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PCI_SPEED_UNKNOWN = 0xff,
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};
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@ -1077,6 +1078,10 @@ int pcie_get_mps(struct pci_dev *dev);
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int pcie_set_mps(struct pci_dev *dev, int mps);
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int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
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enum pcie_link_width *width);
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u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
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enum pci_bus_speed *speed,
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enum pcie_link_width *width);
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void pcie_print_link_status(struct pci_dev *dev);
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void pcie_flr(struct pci_dev *dev);
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int __pci_reset_function_locked(struct pci_dev *dev);
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int pci_reset_function(struct pci_dev *dev);
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