iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

i2c: xiic: Add wait for FIFO empty in send_tx

Browse Source 
If the tx_half_empty interrupt comes first instead of tx_empty,
STOP bit is generated even before all the bytes are transmitted
out on the bus.
STOP bit should be sent only after all the bytes in the FIFO are
transmitted out of the FIFO. So wait until FIFO is empty before sending
the STOP bit.

Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Raviteja Narayanam 2023-02-02 15:11:33 +05:30 committed by Wolfram Sang
parent 2fd5cf352e
commit 317b56c9aa
1 changed files with 7 additions and 0 deletions

7
drivers/i2c/busses/i2c-xiic.c

@ -436,6 +436,13 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
data |= XIIC_TX_DYN_STOP_MASK;
} else {
u8 cr;
int status;
/* Wait till FIFO is empty so STOP is sent last */
status = xiic_wait_tx_empty(i2c);
if (status)
return;
/* Write to CR to stop */
cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &