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drm/i915: invalidate render cache on gen2

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It looks like we also need to flush the render cache when we just
invalidate it. This fixes a regression in i-g-t/gem_tiled_blits on my
i855gm. I guess the render cache there is virtually indexed, so we
need to clean it when changing gtt mappings.

This regression has been introduce in

commit 46f0f8d120c4afae53a5670bf3ac80a928340ff3
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed Apr 18 11:12:11 2012 +0100

    drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2012-04-19 16:45:22 +02:00
parent 284d5df571
commit 31b14c9fc5
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_ringbuffer.c
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@ -61,7 +61,7 @@ gen2_render_ring_flush(struct intel_ring_buffer *ring,
int ret;
cmd = MI_FLUSH;
if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
cmd |= MI_NO_WRITE_FLUSH;
if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)