thermal: exynos: Add support for TRIM_RELOAD feature at Exynos3250
This patch add support for TRIM_RELOAD feature at Exynos3250. The TMu of Exynos3250 has two TRIMINFO_CON register and must need to set RELOAD bit before reading TRIMINFO register. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Zhang Rui <rui.zhang@intel.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Reviewed-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
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@ -87,6 +87,9 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
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#if defined(CONFIG_SOC_EXYNOS3250)
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static const struct exynos_tmu_registers exynos3250_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON1,
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.triminfo_ctrl[1] = EXYNOS_TMU_TRIMINFO_CON2,
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.triminfo_ctrl_count = 2,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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@ -147,8 +150,10 @@ static const struct exynos_tmu_registers exynos3250_tmu_registers = {
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.temp_level = 95, \
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}, \
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.freq_tab_count = 2, \
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.triminfo_reload[0] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
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.triminfo_reload[1] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
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.registers = &exynos3250_tmu_registers, \
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.features = (TMU_SUPPORT_EMULATION | \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
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TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
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TMU_SUPPORT_EMUL_TIME)
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#endif
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@ -169,7 +174,7 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
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#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
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static const struct exynos_tmu_registers exynos4412_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON,
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.triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON2,
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.triminfo_ctrl_count = 1,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
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@ -39,14 +39,17 @@
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#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
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#define EXYNOS_TMU_CORE_EN_SHIFT 0
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/* Exynos3250 specific registers */
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#define EXYNOS_TMU_TRIMINFO_CON1 0x10
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/* Exynos4210 specific registers */
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#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
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#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
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#define EXYNOS4210_TMU_TRIG_LEVEL_MASK 0x1111
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/* Exynos5250 and Exynos4412 specific registers */
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#define EXYNOS_TMU_TRIMINFO_CON 0x14
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/* Exynos5250, Exynos4412, Exynos3250 specific registers */
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#define EXYNOS_TMU_TRIMINFO_CON2 0x14
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#define EXYNOS_THD_TEMP_RISE 0x50
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#define EXYNOS_THD_TEMP_FALL 0x54
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#define EXYNOS_EMUL_CON 0x80
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