pwm: atmel-pwm: Add Atmel PWM controller driver
Add a PWM framework driver for the PWM controller found on Atmel SoCs. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> [thierry.reding: coding style and other minor cleanups] Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Bo Shen
Thierry Reding
parent
ca7a97add4
commit
32b16d46e4
@ -41,6 +41,15 @@ config PWM_AB8500
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To compile this driver as a module, choose M here: the module
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will be called pwm-ab8500.
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config PWM_ATMEL
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tristate "Atmel PWM support"
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depends on ARCH_AT91
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help
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Generic PWM framework driver for Atmel SoC.
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To compile this driver as a module, choose M here: the module
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will be called pwm-atmel.
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config PWM_ATMEL_TCB
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tristate "Atmel TC Block PWM support"
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depends on ATMEL_TCLIB && OF
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@ -1,6 +1,7 @@
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obj-$(CONFIG_PWM) += core.o
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obj-$(CONFIG_PWM_SYSFS) += sysfs.o
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obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
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obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
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obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
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obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
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obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o
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393
drivers/pwm/pwm-atmel.c
Normal file
393
drivers/pwm/pwm-atmel.c
Normal file
@ -0,0 +1,393 @@
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/*
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* Driver for Atmel Pulse Width Modulation Controller
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*
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* Copyright (C) 2013 Atmel Corporation
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* Bo Shen <voice.shen@atmel.com>
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*
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* Licensed under GPLv2.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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/* The following is global registers for PWM controller */
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#define PWM_ENA 0x04
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#define PWM_DIS 0x08
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#define PWM_SR 0x0C
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/* Bit field in SR */
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#define PWM_SR_ALL_CH_ON 0x0F
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/* The following register is PWM channel related registers */
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#define PWM_CH_REG_OFFSET 0x200
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#define PWM_CH_REG_SIZE 0x20
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#define PWM_CMR 0x0
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/* Bit field in CMR */
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#define PWM_CMR_CPOL (1 << 9)
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#define PWM_CMR_UPD_CDTY (1 << 10)
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/* The following registers for PWM v1 */
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#define PWMV1_CDTY 0x04
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#define PWMV1_CPRD 0x08
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#define PWMV1_CUPD 0x10
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/* The following registers for PWM v2 */
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#define PWMV2_CDTY 0x04
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#define PWMV2_CDTYUPD 0x08
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#define PWMV2_CPRD 0x0C
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#define PWMV2_CPRDUPD 0x10
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/*
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* Max value for duty and period
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*
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* Although the duty and period register is 32 bit,
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* however only the LSB 16 bits are significant.
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*/
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#define PWM_MAX_DTY 0xFFFF
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#define PWM_MAX_PRD 0xFFFF
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#define PRD_MAX_PRES 10
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struct atmel_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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void __iomem *base;
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void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
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unsigned long dty, unsigned long prd);
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};
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static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct atmel_pwm_chip, chip);
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}
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static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
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unsigned long offset)
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{
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return readl_relaxed(chip->base + offset);
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}
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static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
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unsigned long offset, unsigned long val)
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{
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writel_relaxed(val, chip->base + offset);
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}
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static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
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unsigned int ch, unsigned long offset)
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{
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unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
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return readl_relaxed(chip->base + base + offset);
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}
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static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
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unsigned int ch, unsigned long offset,
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unsigned long val)
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{
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unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
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writel_relaxed(val, chip->base + base + offset);
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}
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static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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unsigned long clk_rate, prd, dty;
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unsigned long long div;
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unsigned int pres = 0;
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int ret;
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if (test_bit(PWMF_ENABLED, &pwm->flags) && (period_ns != pwm->period)) {
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dev_err(chip->dev, "cannot change PWM period while enabled\n");
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return -EBUSY;
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}
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clk_rate = clk_get_rate(atmel_pwm->clk);
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div = clk_rate;
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/* Calculate the period cycles */
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while (div > PWM_MAX_PRD) {
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div = clk_rate / (1 << pres);
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div = div * period_ns;
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/* 1/Hz = 100000000 ns */
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do_div(div, 1000000000);
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if (pres++ > PRD_MAX_PRES) {
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dev_err(chip->dev, "pres exceeds the maximum value\n");
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return -EINVAL;
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}
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}
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/* Calculate the duty cycles */
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prd = div;
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div *= duty_ns;
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do_div(div, period_ns);
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dty = div;
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ret = clk_enable(atmel_pwm->clk);
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if (ret) {
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dev_err(chip->dev, "failed to enable PWM clock\n");
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return ret;
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}
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, pres);
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atmel_pwm->config(chip, pwm, dty, prd);
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clk_disable(atmel_pwm->clk);
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return ret;
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}
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static void atmel_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
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unsigned long dty, unsigned long prd)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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unsigned int val;
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if (test_bit(PWMF_ENABLED, &pwm->flags)) {
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/*
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* If the PWM channel is enabled, using the update register,
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* it needs to set bit 10 of CMR to 0
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*/
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
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val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
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val &= ~PWM_CMR_UPD_CDTY;
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
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} else {
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/*
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* If the PWM channel is disabled, write value to duty and
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* period registers directly.
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*/
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
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}
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}
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static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
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unsigned long dty, unsigned long prd)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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if (test_bit(PWMF_ENABLED, &pwm->flags)) {
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/*
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* If the PWM channel is enabled, using the duty update register
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* to update the value.
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*/
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTYUPD, dty);
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} else {
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/*
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* If the PWM channel is disabled, write value to duty and
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* period registers directly.
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*/
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTY, dty);
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CPRD, prd);
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}
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}
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static int atmel_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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u32 val;
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int ret;
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val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
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if (polarity == PWM_POLARITY_NORMAL)
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val &= ~PWM_CMR_CPOL;
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else
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val |= PWM_CMR_CPOL;
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ret = clk_enable(atmel_pwm->clk);
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if (ret) {
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dev_err(chip->dev, "failed to enable PWM clock\n");
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return ret;
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}
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
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clk_disable(atmel_pwm->clk);
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return 0;
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}
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static int atmel_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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int ret;
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ret = clk_enable(atmel_pwm->clk);
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if (ret) {
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dev_err(chip->dev, "failed to enable PWM clock\n");
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return ret;
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}
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atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
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return 0;
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}
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static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
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clk_disable(atmel_pwm->clk);
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}
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static const struct pwm_ops atmel_pwm_ops = {
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.config = atmel_pwm_config,
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.set_polarity = atmel_pwm_set_polarity,
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.enable = atmel_pwm_enable,
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.disable = atmel_pwm_disable,
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.owner = THIS_MODULE,
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};
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struct atmel_pwm_data {
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void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
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unsigned long dty, unsigned long prd);
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};
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static const struct atmel_pwm_data atmel_pwm_data_v1 = {
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.config = atmel_pwm_config_v1,
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};
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static const struct atmel_pwm_data atmel_pwm_data_v2 = {
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.config = atmel_pwm_config_v2,
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};
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static const struct platform_device_id atmel_pwm_devtypes[] = {
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{
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.name = "at91sam9rl-pwm",
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.driver_data = (kernel_ulong_t)&atmel_pwm_data_v1,
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}, {
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.name = "sama5d3-pwm",
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.driver_data = (kernel_ulong_t)&atmel_pwm_data_v2,
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}, {
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/* sentinel */
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},
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};
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MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
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static const struct of_device_id atmel_pwm_dt_ids[] = {
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{
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.compatible = "atmel,at91sam9rl-pwm",
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.data = &atmel_pwm_data_v1,
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}, {
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.compatible = "atmel,sama5d3-pwm",
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.data = &atmel_pwm_data_v2,
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}, {
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/* sentinel */
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},
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};
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MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
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static inline const struct atmel_pwm_data *
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atmel_pwm_get_driver_data(struct platform_device *pdev)
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{
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if (pdev->dev.of_node) {
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const struct of_device_id *match;
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match = of_match_device(atmel_pwm_dt_ids, &pdev->dev);
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if (!match)
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return NULL;
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return match->data;
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} else {
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const struct platform_device_id *id;
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id = platform_get_device_id(pdev);
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return (struct atmel_pwm_data *)id->driver_data;
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}
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}
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static int atmel_pwm_probe(struct platform_device *pdev)
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{
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const struct atmel_pwm_data *data;
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struct atmel_pwm_chip *atmel_pwm;
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struct resource *res;
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int ret;
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data = atmel_pwm_get_driver_data(pdev);
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if (!data)
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return -ENODEV;
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atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
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if (!atmel_pwm)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(atmel_pwm->base))
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return PTR_ERR(atmel_pwm->base);
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atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(atmel_pwm->clk))
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return PTR_ERR(atmel_pwm->clk);
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ret = clk_prepare(atmel_pwm->clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to prepare PWM clock\n");
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return ret;
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}
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atmel_pwm->chip.dev = &pdev->dev;
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atmel_pwm->chip.ops = &atmel_pwm_ops;
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if (pdev->dev.of_node) {
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atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
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atmel_pwm->chip.of_pwm_n_cells = 3;
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}
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atmel_pwm->chip.base = -1;
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atmel_pwm->chip.npwm = 4;
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atmel_pwm->config = data->config;
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ret = pwmchip_add(&atmel_pwm->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
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goto unprepare_clk;
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}
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platform_set_drvdata(pdev, atmel_pwm);
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unprepare_clk:
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clk_unprepare(atmel_pwm->clk);
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return ret;
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}
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static int atmel_pwm_remove(struct platform_device *pdev)
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{
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struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
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clk_unprepare(atmel_pwm->clk);
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return pwmchip_remove(&atmel_pwm->chip);
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}
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static struct platform_driver atmel_pwm_driver = {
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.driver = {
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.name = "atmel-pwm",
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.of_match_table = of_match_ptr(atmel_pwm_dt_ids),
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},
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.id_table = atmel_pwm_devtypes,
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.probe = atmel_pwm_probe,
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.remove = atmel_pwm_remove,
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};
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module_platform_driver(atmel_pwm_driver);
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MODULE_ALIAS("platform:atmel-pwm");
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MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
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MODULE_DESCRIPTION("Atmel PWM driver");
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MODULE_LICENSE("GPL v2");
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