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arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock

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Add the "timing-adjustment" clock now that we know how it is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay on the MAC side (if needed).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620162347.26159-1-martin.blumenstingl@googlemail.com
This commit is contained in:
Martin Blumenstingl 2020-06-20 18:23:47 +02:00 committed by Kevin Hilman
parent 5273d6cacc
commit 32b5f4b634
4 changed files with 14 additions and 8 deletions
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6
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
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@ -181,8 +181,10 @@
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
<&clkc CLKID_MPLL2>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "stmmaceth", "clkin0", "clkin1",
"timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
status = "disabled";

6
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
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@ -185,8 +185,10 @@
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
<&clkc CLKID_MPLL2>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "stmmaceth", "clkin0", "clkin1",
"timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
status = "disabled";

5
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
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@ -333,8 +333,9 @@
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
<&clkc CLKID_MPLL2>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
};
&gpio_intc {

5
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@ -131,8 +131,9 @@
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
<&clkc CLKID_MPLL2>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
mdio0: mdio {
#address-cells = <1>;