drm/amd/display: add vline time in micro sec to PSR context
[why] The current PSR SU programming margin is fixed base on FHD 60HZ panel. If the resolution and refresh rate become higher, the time of current margin might not cover the programming SU time. [how] Notice that the programming SU time is the same among different panels. Instead of fixing the margin with target line number, change the margin unit to micro second which indicate the time needed for programming SU. Then FW set the margin line number base on the line time and margin time. Signed-off-by: David Zhang <dingchen.zhang@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3274,6 +3274,8 @@ bool dc_link_setup_psr(struct dc_link *link,
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psr_config->su_granularity_required;
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psr_context->su_y_granularity =
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psr_config->su_y_granularity;
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psr_context->line_time_in_us =
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psr_config->line_time_in_us;
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}
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psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
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@ -676,6 +676,7 @@ struct psr_config {
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bool su_granularity_required;
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/* psr2 selective update y granularity capability */
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uint8_t su_y_granularity;
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unsigned int line_time_in_us;
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};
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union dmcu_psr_level {
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@ -783,6 +784,7 @@ struct psr_context {
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bool su_granularity_required;
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/* psr2 selective update y granularity capability */
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uint8_t su_y_granularity;
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unsigned int line_time_in_us;
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};
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struct colorspace_transform {
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@ -340,6 +340,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
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copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
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copy_settings_data->line_capture_indication = 0;
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copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
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copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
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copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
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copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
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