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drm/radeon: switch driver from bo->resv to bo->base.resv

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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20190805140119.7337-12-kraxel@redhat.com
This commit is contained in:
Gerd Hoffmann 2019-08-05 16:01:13 +02:00
parent e532a135d7
commit 336ac942f1
10 changed files with 21 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/radeon/radeon_benchmark.c
View File

@ -122,7 +122,7 @@ static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size,
if (rdev->asic->copy.dma) {
time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
RADEON_BENCHMARK_COPY_DMA, n,
dobj->tbo.resv);
dobj->tbo.base.resv);
if (time < 0)
goto out_cleanup;
if (time > 0)
@ -133,7 +133,7 @@ static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size,
if (rdev->asic->copy.blit) {
time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
RADEON_BENCHMARK_COPY_BLIT, n,
dobj->tbo.resv);
dobj->tbo.base.resv);
if (time < 0)
goto out_cleanup;
if (time > 0)

2
drivers/gpu/drm/radeon/radeon_cs.c
View File

@ -257,7 +257,7 @@ static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
list_for_each_entry(reloc, &p->validated, tv.head) {
struct reservation_object *resv;
resv = reloc->robj->tbo.resv;
resv = reloc->robj->tbo.base.resv;
r = radeon_sync_resv(p->rdev, &p->ib.sync, resv,
reloc->tv.num_shared);
if (r)

2
drivers/gpu/drm/radeon/radeon_display.c
View File

@ -533,7 +533,7 @@ static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
DRM_ERROR("failed to pin new rbo buffer before flip\n");
goto cleanup;
}
work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.base.resv));
radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
radeon_bo_unreserve(new_rbo);

6
drivers/gpu/drm/radeon/radeon_gem.c
View File

@ -114,7 +114,7 @@ static int radeon_gem_set_domain(struct drm_gem_object *gobj,
}
if (domain == RADEON_GEM_DOMAIN_CPU) {
/* Asking for cpu access wait for object idle */
r = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
r = reservation_object_wait_timeout_rcu(robj->tbo.base.resv, true, true, 30 * HZ);
if (!r)
r = -EBUSY;
@ -449,7 +449,7 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
}
robj = gem_to_radeon_bo(gobj);
r = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
r = reservation_object_test_signaled_rcu(robj->tbo.base.resv, true);
if (r == 0)
r = -EBUSY;
else
@ -478,7 +478,7 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
}
robj = gem_to_radeon_bo(gobj);
ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
ret = reservation_object_wait_timeout_rcu(robj->tbo.base.resv, true, true, 30 * HZ);
if (ret == 0)
r = -EBUSY;
else if (ret < 0)

2
drivers/gpu/drm/radeon/radeon_mn.c
View File

@ -163,7 +163,7 @@ static int radeon_mn_invalidate_range_start(struct mmu_notifier *mn,
continue;
}
r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
r = reservation_object_wait_timeout_rcu(bo->tbo.base.resv,
true, false, MAX_SCHEDULE_TIMEOUT);
if (r <= 0)
DRM_ERROR("(%ld) failed to wait for user bo\n", r);

9
drivers/gpu/drm/radeon/radeon_object.c
View File

@ -262,7 +262,6 @@ int radeon_bo_create(struct radeon_device *rdev,
r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
&bo->placement, page_align, !kernel, acc_size,
sg, resv, &radeon_ttm_bo_destroy);
bo->tbo.base.resv = bo->tbo.resv;
up_read(&rdev->pm.mclk_lock);
if (unlikely(r != 0)) {
return r;
@ -611,7 +610,7 @@ int radeon_bo_get_surface_reg(struct radeon_bo *bo)
int steal;
int i;
reservation_object_assert_held(bo->tbo.resv);
reservation_object_assert_held(bo->tbo.base.resv);
if (!bo->tiling_flags)
return 0;
@ -737,7 +736,7 @@ void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
uint32_t *tiling_flags,
uint32_t *pitch)
{
reservation_object_assert_held(bo->tbo.resv);
reservation_object_assert_held(bo->tbo.base.resv);
if (tiling_flags)
*tiling_flags = bo->tiling_flags;
@ -749,7 +748,7 @@ int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
bool force_drop)
{
if (!force_drop)
reservation_object_assert_held(bo->tbo.resv);
reservation_object_assert_held(bo->tbo.base.resv);
if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
return 0;
@ -871,7 +870,7 @@ int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
bool shared)
{
struct reservation_object *resv = bo->tbo.resv;
struct reservation_object *resv = bo->tbo.base.resv;
if (shared)
reservation_object_add_shared_fence(resv, &fence->base);

8
drivers/gpu/drm/radeon/radeon_test.c
View File

@ -120,11 +120,11 @@ static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
if (ring == R600_RING_TYPE_DMA_INDEX)
fence = radeon_copy_dma(rdev, gtt_addr, vram_addr,
size / RADEON_GPU_PAGE_SIZE,
vram_obj->tbo.resv);
vram_obj->tbo.base.resv);
else
fence = radeon_copy_blit(rdev, gtt_addr, vram_addr,
size / RADEON_GPU_PAGE_SIZE,
vram_obj->tbo.resv);
vram_obj->tbo.base.resv);
if (IS_ERR(fence)) {
DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
r = PTR_ERR(fence);
@ -171,11 +171,11 @@ static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
if (ring == R600_RING_TYPE_DMA_INDEX)
fence = radeon_copy_dma(rdev, vram_addr, gtt_addr,
size / RADEON_GPU_PAGE_SIZE,
vram_obj->tbo.resv);
vram_obj->tbo.base.resv);
else
fence = radeon_copy_blit(rdev, vram_addr, gtt_addr,
size / RADEON_GPU_PAGE_SIZE,
vram_obj->tbo.resv);
vram_obj->tbo.base.resv);
if (IS_ERR(fence)) {
DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
r = PTR_ERR(fence);

2
drivers/gpu/drm/radeon/radeon_ttm.c
View File

@ -244,7 +244,7 @@ static int radeon_move_blit(struct ttm_buffer_object *bo,
BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv);
if (IS_ERR(fence))
return PTR_ERR(fence);

2
drivers/gpu/drm/radeon/radeon_uvd.c
View File

@ -477,7 +477,7 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
return -EINVAL;
}
f = reservation_object_get_excl(bo->tbo.resv);
f = reservation_object_get_excl(bo->tbo.base.resv);
if (f) {
r = radeon_fence_wait((struct radeon_fence *)f, false);
if (r) {

6
drivers/gpu/drm/radeon/radeon_vm.c
View File

@ -702,7 +702,7 @@ int radeon_vm_update_page_directory(struct radeon_device *rdev,
if (ib.length_dw != 0) {
radeon_asic_vm_pad_ib(rdev, &ib);
radeon_sync_resv(rdev, &ib.sync, pd->tbo.resv, true);
radeon_sync_resv(rdev, &ib.sync, pd->tbo.base.resv, true);
WARN_ON(ib.length_dw > ndw);
r = radeon_ib_schedule(rdev, &ib, NULL, false);
if (r) {
@ -830,8 +830,8 @@ static int radeon_vm_update_ptes(struct radeon_device *rdev,
uint64_t pte;
int r;
radeon_sync_resv(rdev, &ib->sync, pt->tbo.resv, true);
r = reservation_object_reserve_shared(pt->tbo.resv, 1);
radeon_sync_resv(rdev, &ib->sync, pt->tbo.base.resv, true);
r = reservation_object_reserve_shared(pt->tbo.base.resv, 1);
if (r)
return r;