ARM: SoC platform updates for v4.6
Newly added support for additional SoCs: - Axis Artpec-6 SoC family - Allwinner A83T SoC - Mediatek MT7623 - NXP i.MX6QP SoC - ST Microelectronics stm32f469 microcontroller New features: - SMP support for Mediatek mt2701 - Big-endian support for NXP i.MX - DaVinci now uses the new DMA engine dma_slave_map - OMAP now uses the new DMA engine dma_slave_map - earlyprintk support for palmchip uart on mach-tango - delay timer support for orion Other: - Exynos PMU driver moved out to drivers/soc/ - Various smaller updates for Renesas, Xilinx, PXA, AT91, OMAP, uniphier -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUAVu68DGCrR//JCVInAQIHVQ//Wblms+NKj3aKh6m2Sscs/YkSbFaQ4sY2 rNyfxLIYsLXkth1kbdHRFSMyL68Ym+xutErgw/3HQPB2D1YtYJE3VJ/y8AU92SU3 oHyQIty+atB8d8zBbtlkWmat94NIfYf0I8PQETreGb1LMaJqAf0mDEDAyorTLZcZ UtQ817Ihn7urqwdTJpTO58V41RmY/vflbHI5T6bIjUJn6fF1e/7+VqtMIfq5sjJ6 0EPEQdu8s5AJ7gcGlGi9I5gAtSnWSA/9phAxul9P8/HrMpUWIxreSEAy8FY7W14F 4TON3sQrnw7nyA72U80KGIXhgLy7SbEmHcSqyy4YJK3ycdk6VYk0CBO7nWVYAiD1 knLisOH6jwe0LIj9WXiRR+Y2Q53pXN8SF77pLDahSnvuShnYEjEH5uELHtxe7Vxh gn+NH1rDkRTgdYgt4RWlVyUoLkddQWzLb1m4QyQlvxtTR25cJJayXdVX2MRrNPF5 c1zRa9HH+b8LJQIMdWfo/NoHhHtftkkGGsqHAAaypZqdpyk0j2HpJYk5ecPR4f5C /8o/h/5xOI9gEzp/DVYSZ1VAvRqBQGIDfKBXWq6GuoZaF0aN8ISe5IxFn5Yx2F46 fNaxqiNpWmyywl8D+tSWPFK6aE21AXKGi5zIzexZZqy283aDjlUPI+tgF2GKIuKP 3ayYTDeBpLI= =ynNj -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Arnd Bergmann: "Newly added support for additional SoCs: - Axis Artpec-6 SoC family - Allwinner A83T SoC - Mediatek MT7623 - NXP i.MX6QP SoC - ST Microelectronics stm32f469 microcontroller New features: - SMP support for Mediatek mt2701 - Big-endian support for NXP i.MX - DaVinci now uses the new DMA engine dma_slave_map - OMAP now uses the new DMA engine dma_slave_map - earlyprintk support for palmchip uart on mach-tango - delay timer support for orion Other: - Exynos PMU driver moved out to drivers/soc/ - Various smaller updates for Renesas, Xilinx, PXA, AT91, OMAP, uniphier" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: uniphier: rework SMP code to support new System Bus binding ARM: uniphier: add missing of_node_put() ARM: at91: avoid defining CONFIG_* symbols in source code ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1 ARM: imx: Make reset_control_ops const ARM: imx: Do L2 errata only if the L2 cache isn't enabled ARM: imx: select ARM_CPU_SUSPEND only for imx6 dmaengine: pxa_dma: fix the maximum requestor line ARM: alpine: select the Alpine MSI controller driver ARM: pxa: add the number of DMA requestor lines dmaengine: mmp-pdma: add number of requestors dma: mmp_pdma: Add the #dma-requests DT property documentation ARM: OMAP2+: Add rtc hwmod configuration for ti81xx ARM: s3c24xx: Avoid warning for inb/outb ARM: zynq: Move early printk virtual address to vmalloc area ARM: DRA7: hwmod: Add custom reset handler for PCIeSS ARM: SAMSUNG: Remove unused register offset definition ARM: EXYNOS: Cleanup header files inclusion drivers: soc: samsung: Enable COMPILE_TEST MAINTAINERS: Add maintainers entry for drivers/soc/samsung ...
This commit is contained in:
commit
33b3d2e88c
@ -72,6 +72,5 @@ SunXi family
|
|||||||
|
|
||||||
* Octa ARM Cortex-A7 based SoCs
|
* Octa ARM Cortex-A7 based SoCs
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||||||
- Allwinner A83T
|
- Allwinner A83T
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||||||
+ Not Supported
|
|
||||||
+ Datasheet
|
+ Datasheet
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||||||
http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf
|
http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf
|
||||||
|
@ -11,5 +11,6 @@ using one of the following compatible strings:
|
|||||||
allwinner,sun7i-a20
|
allwinner,sun7i-a20
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||||||
allwinner,sun8i-a23
|
allwinner,sun8i-a23
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||||||
allwinner,sun8i-a33
|
allwinner,sun8i-a33
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||||||
|
allwinner,sun8i-a83t
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||||||
allwinner,sun8i-h3
|
allwinner,sun8i-h3
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||||||
allwinner,sun9i-a80
|
allwinner,sun9i-a80
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||||||
|
@ -12,6 +12,8 @@ Required properties:
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|||||||
Optional properties:
|
Optional properties:
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||||||
- #dma-channels: Number of DMA channels supported by the controller (defaults
|
- #dma-channels: Number of DMA channels supported by the controller (defaults
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||||||
to 32 when not specified)
|
to 32 when not specified)
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||||||
|
- #dma-requests: Number of DMA requestor lines supported by the controller
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|
(defaults to 32 when not specified)
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|
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"marvell,pdma-1.0"
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"marvell,pdma-1.0"
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||||||
Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
|
Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
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||||||
|
16
MAINTAINERS
16
MAINTAINERS
@ -951,6 +951,16 @@ F: arch/arm/boot/dts/alpine*
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|||||||
F: arch/arm64/boot/dts/al/
|
F: arch/arm64/boot/dts/al/
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F: drivers/*/*alpine*
|
F: drivers/*/*alpine*
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||||||
|
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||||||
|
ARM/ARTPEC MACHINE SUPPORT
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|
M: Jesper Nilsson <jesper.nilsson@axis.com>
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|
M: Lars Persson <lars.persson@axis.com>
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||||||
|
M: Niklas Cassel <niklas.cassel@axis.com>
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||||||
|
S: Maintained
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||||||
|
L: linux-arm-kernel@axis.com
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||||||
|
F: arch/arm/mach-artpec
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||||||
|
F: arch/arm/boot/dts/artpec6*
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||||||
|
F: drivers/clk/clk-artpec6.c
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||||||
|
|
||||||
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
|
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
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M: Nicolas Ferre <nicolas.ferre@atmel.com>
|
M: Nicolas Ferre <nicolas.ferre@atmel.com>
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||||||
M: Alexandre Belloni <alexandre.belloni@free-electrons.com>
|
M: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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@ -1515,6 +1525,7 @@ F: arch/arm/mach-s5p*/
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F: arch/arm/mach-exynos*/
|
F: arch/arm/mach-exynos*/
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F: drivers/*/*s3c2410*
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F: drivers/*/*s3c2410*
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F: drivers/*/*/*s3c2410*
|
F: drivers/*/*/*s3c2410*
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|
F: drivers/soc/samsung/*
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F: drivers/spi/spi-s3c*
|
F: drivers/spi/spi-s3c*
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F: sound/soc/samsung/*
|
F: sound/soc/samsung/*
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||||||
F: Documentation/arm/Samsung/
|
F: Documentation/arm/Samsung/
|
||||||
@ -2406,8 +2417,9 @@ F: arch/arm/boot/dts/bcm470*
|
|||||||
|
|
||||||
BROADCOM BCM63XX ARM ARCHITECTURE
|
BROADCOM BCM63XX ARM ARCHITECTURE
|
||||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||||
L: linux-arm-kernel@lists.infradead.org
|
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||||
T: git git://github.com/broadcom/arm-bcm63xx.git
|
L: bcm-kernel-feedback-list@broadcom.com
|
||||||
|
T: git git://github.com/broadcom/stblinux.git
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||||||
S: Maintained
|
S: Maintained
|
||||||
F: arch/arm/mach-bcm/bcm63xx.c
|
F: arch/arm/mach-bcm/bcm63xx.c
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||||||
F: arch/arm/include/debug/bcm63xx.S
|
F: arch/arm/include/debug/bcm63xx.S
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||||||
|
@ -547,6 +547,7 @@ config ARCH_PXA
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select CLKSRC_PXA
|
select CLKSRC_PXA
|
||||||
select CLKSRC_MMIO
|
select CLKSRC_MMIO
|
||||||
select CLKSRC_OF
|
select CLKSRC_OF
|
||||||
|
select CPU_XSCALE if !CPU_XSC3
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||||||
select GENERIC_CLOCKEVENTS
|
select GENERIC_CLOCKEVENTS
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||||||
select GPIO_PXA
|
select GPIO_PXA
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||||||
select HAVE_IDE
|
select HAVE_IDE
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||||||
@ -724,6 +725,8 @@ source "arch/arm/mach-mvebu/Kconfig"
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|||||||
|
|
||||||
source "arch/arm/mach-alpine/Kconfig"
|
source "arch/arm/mach-alpine/Kconfig"
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||||||
|
|
||||||
|
source "arch/arm/mach-artpec/Kconfig"
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||||||
|
|
||||||
source "arch/arm/mach-asm9260/Kconfig"
|
source "arch/arm/mach-asm9260/Kconfig"
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||||||
|
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||||||
source "arch/arm/mach-at91/Kconfig"
|
source "arch/arm/mach-at91/Kconfig"
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||||||
@ -879,10 +882,16 @@ config ARCH_STM32
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|||||||
select ARCH_HAS_RESET_CONTROLLER
|
select ARCH_HAS_RESET_CONTROLLER
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||||||
select ARMV7M_SYSTICK
|
select ARMV7M_SYSTICK
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||||||
select CLKSRC_STM32
|
select CLKSRC_STM32
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|
select PINCTRL
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||||||
select RESET_CONTROLLER
|
select RESET_CONTROLLER
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||||||
help
|
help
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||||||
Support for STMicroelectronics STM32 processors.
|
Support for STMicroelectronics STM32 processors.
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|
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||||||
|
config MACH_STM32F429
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|
bool "STMicrolectronics STM32F429"
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||||||
|
depends on ARCH_STM32
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||||||
|
default y
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||||||
|
|
||||||
# Definitions to make life easier
|
# Definitions to make life easier
|
||||||
config ARCH_ACORN
|
config ARCH_ACORN
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||||||
bool
|
bool
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||||||
|
@ -1368,6 +1368,7 @@ config DEBUG_SIRFSOC_UART
|
|||||||
config DEBUG_LL_INCLUDE
|
config DEBUG_LL_INCLUDE
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||||||
string
|
string
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||||||
default "debug/sa1100.S" if DEBUG_SA1100
|
default "debug/sa1100.S" if DEBUG_SA1100
|
||||||
|
default "debug/palmchip.S" if DEBUG_UART_8250_PALMCHIP
|
||||||
default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
|
default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
|
||||||
default "debug/at91.S" if DEBUG_AT91_UART
|
default "debug/at91.S" if DEBUG_AT91_UART
|
||||||
default "debug/asm9260.S" if DEBUG_ASM9260_UART
|
default "debug/asm9260.S" if DEBUG_ASM9260_UART
|
||||||
@ -1656,6 +1657,14 @@ config DEBUG_UART_8250_WORD
|
|||||||
DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \
|
DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \
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||||||
DEBUG_BRCMSTB_UART
|
DEBUG_BRCMSTB_UART
|
||||||
|
|
||||||
|
config DEBUG_UART_8250_PALMCHIP
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||||||
|
bool "8250 UART is Palmchip BK-310x"
|
||||||
|
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
|
||||||
|
help
|
||||||
|
Palmchip provides a UART implementation compatible with 16550
|
||||||
|
except for having a different register layout. Say Y here if
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||||||
|
the debug UART is of this type.
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||||||
|
|
||||||
config DEBUG_UART_8250_FLOW_CONTROL
|
config DEBUG_UART_8250_FLOW_CONTROL
|
||||||
bool "Enable flow control for 8250 UART"
|
bool "Enable flow control for 8250 UART"
|
||||||
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
|
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
|
||||||
|
@ -154,6 +154,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
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|||||||
# Machine directory name. This list is sorted alphanumerically
|
# Machine directory name. This list is sorted alphanumerically
|
||||||
# by CONFIG_* macro name.
|
# by CONFIG_* macro name.
|
||||||
machine-$(CONFIG_ARCH_ALPINE) += alpine
|
machine-$(CONFIG_ARCH_ALPINE) += alpine
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||||||
|
machine-$(CONFIG_ARCH_ARTPEC) += artpec
|
||||||
machine-$(CONFIG_ARCH_AT91) += at91
|
machine-$(CONFIG_ARCH_AT91) += at91
|
||||||
machine-$(CONFIG_ARCH_AXXIA) += axxia
|
machine-$(CONFIG_ARCH_AXXIA) += axxia
|
||||||
machine-$(CONFIG_ARCH_BCM) += bcm
|
machine-$(CONFIG_ARCH_BCM) += bcm
|
||||||
|
@ -13,6 +13,7 @@
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|||||||
interrupts = <25>;
|
interrupts = <25>;
|
||||||
#dma-channels = <32>;
|
#dma-channels = <32>;
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||||||
#dma-cells = <2>;
|
#dma-cells = <2>;
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||||||
|
#dma-requests = <75>;
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status = "okay";
|
status = "okay";
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};
|
};
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|
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||||||
|
@ -12,6 +12,7 @@
|
|||||||
interrupts = <25>;
|
interrupts = <25>;
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#dma-channels = <32>;
|
#dma-channels = <32>;
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#dma-cells = <2>;
|
#dma-cells = <2>;
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||||||
|
#dma-requests = <100>;
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||||||
status = "okay";
|
status = "okay";
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||||||
};
|
};
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||||||
|
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||||||
|
@ -378,6 +378,7 @@ CONFIG_GPIO_PALMAS=y
|
|||||||
CONFIG_GPIO_TPS6586X=y
|
CONFIG_GPIO_TPS6586X=y
|
||||||
CONFIG_GPIO_TPS65910=y
|
CONFIG_GPIO_TPS65910=y
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CONFIG_GPIO_MAX7301=m
|
CONFIG_GPIO_MAX7301=m
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||||||
|
CONFIG_GPIO_SYSFS=y
|
||||||
CONFIG_POWER_SUPPLY_DEBUG=y
|
CONFIG_POWER_SUPPLY_DEBUG=y
|
||||||
CONFIG_PDA_POWER=m
|
CONFIG_PDA_POWER=m
|
||||||
CONFIG_BATTERY_SBS=m
|
CONFIG_BATTERY_SBS=m
|
||||||
|
@ -15,7 +15,7 @@
|
|||||||
#define AT91_IO_P2V(x) (x)
|
#define AT91_IO_P2V(x) (x)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_DEBUG_UART_VIRT AT91_IO_P2V(CONFIG_DEBUG_UART_PHYS)
|
#define AT91_DEBUG_UART_VIRT AT91_IO_P2V(CONFIG_DEBUG_UART_PHYS)
|
||||||
|
|
||||||
#define AT91_DBGU_SR (0x14) /* Status Register */
|
#define AT91_DBGU_SR (0x14) /* Status Register */
|
||||||
#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
|
#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
|
||||||
@ -24,7 +24,7 @@
|
|||||||
|
|
||||||
.macro addruart, rp, rv, tmp
|
.macro addruart, rp, rv, tmp
|
||||||
ldr \rp, =CONFIG_DEBUG_UART_PHYS @ System peripherals (phys address)
|
ldr \rp, =CONFIG_DEBUG_UART_PHYS @ System peripherals (phys address)
|
||||||
ldr \rv, =CONFIG_DEBUG_UART_VIRT @ System peripherals (virt address)
|
ldr \rv, =AT91_DEBUG_UART_VIRT @ System peripherals (virt address)
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro senduart,rd,rx
|
.macro senduart,rd,rx
|
||||||
|
@ -11,6 +11,7 @@
|
|||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <asm/assembler.h>
|
||||||
#include "imx-uart.h"
|
#include "imx-uart.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -34,6 +35,7 @@
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro senduart,rd,rx
|
.macro senduart,rd,rx
|
||||||
|
ARM_BE8(rev \rd, \rd)
|
||||||
str \rd, [\rx, #0x40] @ TXDATA
|
str \rd, [\rx, #0x40] @ TXDATA
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
@ -42,6 +44,7 @@
|
|||||||
|
|
||||||
.macro busyuart,rd,rx
|
.macro busyuart,rd,rx
|
||||||
1002: ldr \rd, [\rx, #0x98] @ SR2
|
1002: ldr \rd, [\rx, #0x98] @ SR2
|
||||||
|
ARM_BE8(rev \rd, \rd)
|
||||||
tst \rd, #1 << 3 @ TXDC
|
tst \rd, #1 << 3 @ TXDC
|
||||||
beq 1002b @ wait until transmit done
|
beq 1002b @ wait until transmit done
|
||||||
.endm
|
.endm
|
||||||
|
11
arch/arm/include/debug/palmchip.S
Normal file
11
arch/arm/include/debug/palmchip.S
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
#include <linux/serial_reg.h>
|
||||||
|
|
||||||
|
#undef UART_TX
|
||||||
|
#undef UART_LSR
|
||||||
|
#undef UART_MSR
|
||||||
|
|
||||||
|
#define UART_TX 1
|
||||||
|
#define UART_LSR 7
|
||||||
|
#define UART_MSR 8
|
||||||
|
|
||||||
|
#include <debug/8250.S>
|
@ -20,9 +20,9 @@
|
|||||||
#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
|
#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
|
||||||
|
|
||||||
#define UART0_PHYS 0xE0000000
|
#define UART0_PHYS 0xE0000000
|
||||||
#define UART0_VIRT 0xF0000000
|
#define UART0_VIRT 0xF0800000
|
||||||
#define UART1_PHYS 0xE0001000
|
#define UART1_PHYS 0xE0001000
|
||||||
#define UART1_VIRT 0xF0001000
|
#define UART1_VIRT 0xF0801000
|
||||||
|
|
||||||
#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
|
#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
|
||||||
# define LL_UART_PADDR UART1_PHYS
|
# define LL_UART_PADDR UART1_PHYS
|
||||||
|
@ -1,6 +1,7 @@
|
|||||||
config ARCH_ALPINE
|
config ARCH_ALPINE
|
||||||
bool "Annapurna Labs Alpine platform"
|
bool "Annapurna Labs Alpine platform"
|
||||||
depends on ARCH_MULTI_V7
|
depends on ARCH_MULTI_V7
|
||||||
|
select ALPINE_MSI
|
||||||
select ARM_AMBA
|
select ARM_AMBA
|
||||||
select ARM_GIC
|
select ARM_GIC
|
||||||
select GENERIC_IRQ_CHIP
|
select GENERIC_IRQ_CHIP
|
||||||
|
20
arch/arm/mach-artpec/Kconfig
Normal file
20
arch/arm/mach-artpec/Kconfig
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
menuconfig ARCH_ARTPEC
|
||||||
|
bool "Axis Communications ARM based ARTPEC SoCs"
|
||||||
|
depends on ARCH_MULTI_V7
|
||||||
|
|
||||||
|
if ARCH_ARTPEC
|
||||||
|
|
||||||
|
config MACH_ARTPEC6
|
||||||
|
bool "Axis ARTPEC-6 ARM Cortex A9 Platform"
|
||||||
|
depends on ARCH_MULTI_V7
|
||||||
|
select ARM_AMBA
|
||||||
|
select ARM_GIC
|
||||||
|
select ARM_GLOBAL_TIMER
|
||||||
|
select ARM_PSCI
|
||||||
|
select HAVE_ARM_ARCH_TIMER
|
||||||
|
select HAVE_ARM_SCU
|
||||||
|
select HAVE_ARM_TWD if SMP
|
||||||
|
help
|
||||||
|
Support for Axis ARTPEC-6 ARM Cortex A9 Platform
|
||||||
|
|
||||||
|
endif
|
1
arch/arm/mach-artpec/Makefile
Normal file
1
arch/arm/mach-artpec/Makefile
Normal file
@ -0,0 +1 @@
|
|||||||
|
obj-$(CONFIG_MACH_ARTPEC6) := board-artpec6.o
|
72
arch/arm/mach-artpec/board-artpec6.c
Normal file
72
arch/arm/mach-artpec/board-artpec6.c
Normal file
@ -0,0 +1,72 @@
|
|||||||
|
/*
|
||||||
|
* ARTPEC-6 device support.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/amba/bus.h>
|
||||||
|
#include <linux/clocksource.h>
|
||||||
|
#include <linux/dma-mapping.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
#include <linux/irqchip.h>
|
||||||
|
#include <linux/irqchip/arm-gic.h>
|
||||||
|
#include <linux/mfd/syscon.h>
|
||||||
|
#include <linux/of_platform.h>
|
||||||
|
#include <linux/of.h>
|
||||||
|
#include <linux/of_address.h>
|
||||||
|
#include <linux/clk-provider.h>
|
||||||
|
#include <linux/regmap.h>
|
||||||
|
#include <linux/smp.h>
|
||||||
|
#include <asm/smp_scu.h>
|
||||||
|
#include <asm/mach/arch.h>
|
||||||
|
#include <asm/mach/map.h>
|
||||||
|
#include <asm/psci.h>
|
||||||
|
#include <linux/arm-smccc.h>
|
||||||
|
|
||||||
|
|
||||||
|
#define ARTPEC6_DMACFG_REGNUM 0x10
|
||||||
|
#define ARTPEC6_DMACFG_UARTS_BURST 0xff
|
||||||
|
|
||||||
|
#define SECURE_OP_L2C_WRITEREG 0xb4000001
|
||||||
|
|
||||||
|
static void __init artpec6_init_machine(void)
|
||||||
|
{
|
||||||
|
struct regmap *regmap;
|
||||||
|
|
||||||
|
regmap = syscon_regmap_lookup_by_compatible("axis,artpec6-syscon");
|
||||||
|
|
||||||
|
if (!IS_ERR(regmap)) {
|
||||||
|
/* Use PL011 DMA Burst Request signal instead of DMA
|
||||||
|
* Single Request
|
||||||
|
*/
|
||||||
|
regmap_write(regmap, ARTPEC6_DMACFG_REGNUM,
|
||||||
|
ARTPEC6_DMACFG_UARTS_BURST);
|
||||||
|
};
|
||||||
|
|
||||||
|
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void artpec6_l2c310_write_sec(unsigned long val, unsigned reg)
|
||||||
|
{
|
||||||
|
struct arm_smccc_res res;
|
||||||
|
|
||||||
|
arm_smccc_smc(SECURE_OP_L2C_WRITEREG, reg, val, 0,
|
||||||
|
0, 0, 0, 0, &res);
|
||||||
|
|
||||||
|
WARN_ON(res.a0);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char * const artpec6_dt_match[] = {
|
||||||
|
"axis,artpec6",
|
||||||
|
NULL
|
||||||
|
};
|
||||||
|
|
||||||
|
DT_MACHINE_START(ARTPEC6, "Axis ARTPEC-6 Platform")
|
||||||
|
.l2c_aux_val = 0x0C000000,
|
||||||
|
.l2c_aux_mask = 0xF3FFFFFF,
|
||||||
|
.l2c_write_sec = artpec6_l2c310_write_sec,
|
||||||
|
.init_machine = artpec6_init_machine,
|
||||||
|
.dt_compat = artpec6_dt_match,
|
||||||
|
MACHINE_END
|
@ -92,7 +92,6 @@ static int bcm63xx_pmb_get_resources(struct device_node *dn,
|
|||||||
unsigned int *cpu,
|
unsigned int *cpu,
|
||||||
unsigned int *addr)
|
unsigned int *addr)
|
||||||
{
|
{
|
||||||
struct device_node *pmb_dn;
|
|
||||||
struct of_phandle_args args;
|
struct of_phandle_args args;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
@ -109,7 +108,6 @@ static int bcm63xx_pmb_get_resources(struct device_node *dn,
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
pmb_dn = args.np;
|
|
||||||
if (args.args_count != 2) {
|
if (args.args_count != 2) {
|
||||||
pr_err("reset-controller does not conform to reset-cells\n");
|
pr_err("reset-controller does not conform to reset-cells\n");
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
@ -283,7 +283,7 @@ static const struct smp_operations bcm_smp_ops __initconst = {
|
|||||||
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
|
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
|
||||||
&bcm_smp_ops);
|
&bcm_smp_ops);
|
||||||
|
|
||||||
struct smp_operations nsp_smp_ops __initdata = {
|
static const struct smp_operations nsp_smp_ops __initconst = {
|
||||||
.smp_prepare_cpus = bcm_smp_prepare_cpus,
|
.smp_prepare_cpus = bcm_smp_prepare_cpus,
|
||||||
.smp_boot_secondary = nsp_boot_secondary,
|
.smp_boot_secondary = nsp_boot_secondary,
|
||||||
};
|
};
|
||||||
|
@ -17,6 +17,7 @@
|
|||||||
#include <linux/ahci_platform.h>
|
#include <linux/ahci_platform.h>
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/reboot.h>
|
#include <linux/reboot.h>
|
||||||
|
#include <linux/dmaengine.h>
|
||||||
|
|
||||||
#include <mach/cputype.h>
|
#include <mach/cputype.h>
|
||||||
#include <mach/common.h>
|
#include <mach/common.h>
|
||||||
@ -233,16 +234,54 @@ static const struct platform_device_info da850_edma1_device __initconst = {
|
|||||||
.size_data = sizeof(da850_edma1_pdata),
|
.size_data = sizeof(da850_edma1_pdata),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct dma_slave_map da830_edma_map[] = {
|
||||||
|
{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
|
||||||
|
{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
|
||||||
|
{ "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
|
||||||
|
{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
|
||||||
|
{ "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
|
||||||
|
{ "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
|
||||||
|
{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
|
||||||
|
{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
|
||||||
|
{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
|
||||||
|
{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
|
||||||
|
{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
|
||||||
|
{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
|
||||||
|
};
|
||||||
|
|
||||||
int __init da830_register_edma(struct edma_rsv_info *rsv)
|
int __init da830_register_edma(struct edma_rsv_info *rsv)
|
||||||
{
|
{
|
||||||
struct platform_device *edma_pdev;
|
struct platform_device *edma_pdev;
|
||||||
|
|
||||||
da8xx_edma0_pdata.rsv = rsv;
|
da8xx_edma0_pdata.rsv = rsv;
|
||||||
|
|
||||||
|
da8xx_edma0_pdata.slave_map = da830_edma_map;
|
||||||
|
da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
|
||||||
|
|
||||||
edma_pdev = platform_device_register_full(&da8xx_edma0_device);
|
edma_pdev = platform_device_register_full(&da8xx_edma0_device);
|
||||||
return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
|
return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static const struct dma_slave_map da850_edma0_map[] = {
|
||||||
|
{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
|
||||||
|
{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
|
||||||
|
{ "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
|
||||||
|
{ "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
|
||||||
|
{ "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
|
||||||
|
{ "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
|
||||||
|
{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
|
||||||
|
{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
|
||||||
|
{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
|
||||||
|
{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
|
||||||
|
{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
|
||||||
|
{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct dma_slave_map da850_edma1_map[] = {
|
||||||
|
{ "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
|
||||||
|
{ "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
|
||||||
|
};
|
||||||
|
|
||||||
int __init da850_register_edma(struct edma_rsv_info *rsv[2])
|
int __init da850_register_edma(struct edma_rsv_info *rsv[2])
|
||||||
{
|
{
|
||||||
struct platform_device *edma_pdev;
|
struct platform_device *edma_pdev;
|
||||||
@ -252,11 +291,18 @@ int __init da850_register_edma(struct edma_rsv_info *rsv[2])
|
|||||||
da850_edma1_pdata.rsv = rsv[1];
|
da850_edma1_pdata.rsv = rsv[1];
|
||||||
}
|
}
|
||||||
|
|
||||||
|
da8xx_edma0_pdata.slave_map = da850_edma0_map;
|
||||||
|
da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
|
||||||
|
|
||||||
edma_pdev = platform_device_register_full(&da8xx_edma0_device);
|
edma_pdev = platform_device_register_full(&da8xx_edma0_device);
|
||||||
if (IS_ERR(edma_pdev)) {
|
if (IS_ERR(edma_pdev)) {
|
||||||
pr_warn("%s: Failed to register eDMA0\n", __func__);
|
pr_warn("%s: Failed to register eDMA0\n", __func__);
|
||||||
return PTR_ERR(edma_pdev);
|
return PTR_ERR(edma_pdev);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
da850_edma1_pdata.slave_map = da850_edma1_map;
|
||||||
|
da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
|
||||||
|
|
||||||
edma_pdev = platform_device_register_full(&da850_edma1_device);
|
edma_pdev = platform_device_register_full(&da850_edma1_device);
|
||||||
return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
|
return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
|
||||||
}
|
}
|
||||||
|
@ -13,6 +13,7 @@
|
|||||||
#include <linux/serial_8250.h>
|
#include <linux/serial_8250.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/dma-mapping.h>
|
#include <linux/dma-mapping.h>
|
||||||
|
#include <linux/dmaengine.h>
|
||||||
#include <linux/spi/spi.h>
|
#include <linux/spi/spi.h>
|
||||||
#include <linux/platform_data/edma.h>
|
#include <linux/platform_data/edma.h>
|
||||||
#include <linux/platform_data/gpio-davinci.h>
|
#include <linux/platform_data/gpio-davinci.h>
|
||||||
@ -576,9 +577,28 @@ static s8 queue_priority_mapping[][2] = {
|
|||||||
{-1, -1},
|
{-1, -1},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct dma_slave_map dm355_edma_map[] = {
|
||||||
|
{ "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
|
||||||
|
{ "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
|
||||||
|
{ "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
|
||||||
|
{ "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
|
||||||
|
{ "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
|
||||||
|
{ "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
|
||||||
|
{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
|
||||||
|
{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
|
||||||
|
{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
|
||||||
|
{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
|
||||||
|
{ "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
|
||||||
|
{ "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
|
||||||
|
{ "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
|
||||||
|
{ "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
|
||||||
|
};
|
||||||
|
|
||||||
static struct edma_soc_info dm355_edma_pdata = {
|
static struct edma_soc_info dm355_edma_pdata = {
|
||||||
.queue_priority_mapping = queue_priority_mapping,
|
.queue_priority_mapping = queue_priority_mapping,
|
||||||
.default_queue = EVENTQ_1,
|
.default_queue = EVENTQ_1,
|
||||||
|
.slave_map = dm355_edma_map,
|
||||||
|
.slavecnt = ARRAY_SIZE(dm355_edma_map),
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource edma_resources[] = {
|
static struct resource edma_resources[] = {
|
||||||
|
@ -17,6 +17,7 @@
|
|||||||
#include <linux/serial_8250.h>
|
#include <linux/serial_8250.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/dma-mapping.h>
|
#include <linux/dma-mapping.h>
|
||||||
|
#include <linux/dmaengine.h>
|
||||||
#include <linux/spi/spi.h>
|
#include <linux/spi/spi.h>
|
||||||
#include <linux/platform_data/edma.h>
|
#include <linux/platform_data/edma.h>
|
||||||
#include <linux/platform_data/gpio-davinci.h>
|
#include <linux/platform_data/gpio-davinci.h>
|
||||||
@ -862,9 +863,30 @@ static s8 dm365_queue_priority_mapping[][2] = {
|
|||||||
{-1, -1},
|
{-1, -1},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct dma_slave_map dm365_edma_map[] = {
|
||||||
|
{ "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
|
||||||
|
{ "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
|
||||||
|
{ "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
|
||||||
|
{ "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
|
||||||
|
{ "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
|
||||||
|
{ "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
|
||||||
|
{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
|
||||||
|
{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
|
||||||
|
{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
|
||||||
|
{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
|
||||||
|
{ "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
|
||||||
|
{ "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
|
||||||
|
{ "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
|
||||||
|
{ "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
|
||||||
|
{ "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
|
||||||
|
{ "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
|
||||||
|
};
|
||||||
|
|
||||||
static struct edma_soc_info dm365_edma_pdata = {
|
static struct edma_soc_info dm365_edma_pdata = {
|
||||||
.queue_priority_mapping = dm365_queue_priority_mapping,
|
.queue_priority_mapping = dm365_queue_priority_mapping,
|
||||||
.default_queue = EVENTQ_3,
|
.default_queue = EVENTQ_3,
|
||||||
|
.slave_map = dm365_edma_map,
|
||||||
|
.slavecnt = ARRAY_SIZE(dm365_edma_map),
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource edma_resources[] = {
|
static struct resource edma_resources[] = {
|
||||||
|
@ -11,6 +11,7 @@
|
|||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/serial_8250.h>
|
#include <linux/serial_8250.h>
|
||||||
|
#include <linux/dmaengine.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/platform_data/edma.h>
|
#include <linux/platform_data/edma.h>
|
||||||
#include <linux/platform_data/gpio-davinci.h>
|
#include <linux/platform_data/gpio-davinci.h>
|
||||||
@ -505,9 +506,20 @@ static s8 queue_priority_mapping[][2] = {
|
|||||||
{-1, -1},
|
{-1, -1},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct dma_slave_map dm644x_edma_map[] = {
|
||||||
|
{ "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
|
||||||
|
{ "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
|
||||||
|
{ "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
|
||||||
|
{ "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
|
||||||
|
{ "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
|
||||||
|
{ "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
|
||||||
|
};
|
||||||
|
|
||||||
static struct edma_soc_info dm644x_edma_pdata = {
|
static struct edma_soc_info dm644x_edma_pdata = {
|
||||||
.queue_priority_mapping = queue_priority_mapping,
|
.queue_priority_mapping = queue_priority_mapping,
|
||||||
.default_queue = EVENTQ_1,
|
.default_queue = EVENTQ_1,
|
||||||
|
.slave_map = dm644x_edma_map,
|
||||||
|
.slavecnt = ARRAY_SIZE(dm644x_edma_map),
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource edma_resources[] = {
|
static struct resource edma_resources[] = {
|
||||||
|
@ -9,6 +9,7 @@
|
|||||||
* or implied.
|
* or implied.
|
||||||
*/
|
*/
|
||||||
#include <linux/dma-mapping.h>
|
#include <linux/dma-mapping.h>
|
||||||
|
#include <linux/dmaengine.h>
|
||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/serial_8250.h>
|
#include <linux/serial_8250.h>
|
||||||
@ -540,9 +541,19 @@ static s8 dm646x_queue_priority_mapping[][2] = {
|
|||||||
{-1, -1},
|
{-1, -1},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct dma_slave_map dm646x_edma_map[] = {
|
||||||
|
{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
|
||||||
|
{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
|
||||||
|
{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
|
||||||
|
{ "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
|
||||||
|
{ "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
|
||||||
|
};
|
||||||
|
|
||||||
static struct edma_soc_info dm646x_edma_pdata = {
|
static struct edma_soc_info dm646x_edma_pdata = {
|
||||||
.queue_priority_mapping = dm646x_queue_priority_mapping,
|
.queue_priority_mapping = dm646x_queue_priority_mapping,
|
||||||
.default_queue = EVENTQ_1,
|
.default_queue = EVENTQ_1,
|
||||||
|
.slave_map = dm646x_edma_map,
|
||||||
|
.slavecnt = ARRAY_SIZE(dm646x_edma_map),
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource edma_resources[] = {
|
static struct resource edma_resources[] = {
|
||||||
|
@ -5,7 +5,7 @@
|
|||||||
#
|
#
|
||||||
# Licensed under GPLv2
|
# Licensed under GPLv2
|
||||||
|
|
||||||
# Configuration options for the EXYNOS4
|
# Configuration options for the EXYNOS
|
||||||
|
|
||||||
menuconfig ARCH_EXYNOS
|
menuconfig ARCH_EXYNOS
|
||||||
bool "Samsung EXYNOS"
|
bool "Samsung EXYNOS"
|
||||||
@ -17,6 +17,7 @@ menuconfig ARCH_EXYNOS
|
|||||||
select ARM_GIC
|
select ARM_GIC
|
||||||
select COMMON_CLK_SAMSUNG
|
select COMMON_CLK_SAMSUNG
|
||||||
select EXYNOS_THERMAL
|
select EXYNOS_THERMAL
|
||||||
|
select EXYNOS_PMU
|
||||||
select HAVE_ARM_SCU if SMP
|
select HAVE_ARM_SCU if SMP
|
||||||
select HAVE_S3C2410_I2C if I2C
|
select HAVE_S3C2410_I2C if I2C
|
||||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||||
@ -25,6 +26,7 @@ menuconfig ARCH_EXYNOS
|
|||||||
select PINCTRL_EXYNOS
|
select PINCTRL_EXYNOS
|
||||||
select PM_GENERIC_DOMAINS if PM
|
select PM_GENERIC_DOMAINS if PM
|
||||||
select S5P_DEV_MFC
|
select S5P_DEV_MFC
|
||||||
|
select SOC_SAMSUNG
|
||||||
select SRAM
|
select SRAM
|
||||||
select THERMAL
|
select THERMAL
|
||||||
select THERMAL_OF
|
select THERMAL_OF
|
||||||
|
@ -9,7 +9,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)
|
|||||||
|
|
||||||
# Core
|
# Core
|
||||||
|
|
||||||
obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o
|
obj-$(CONFIG_ARCH_EXYNOS) += exynos.o exynos-smc.o firmware.o
|
||||||
|
|
||||||
obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o sleep.o
|
obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o sleep.o
|
||||||
obj-$(CONFIG_PM_SLEEP) += suspend.o
|
obj-$(CONFIG_PM_SLEEP) += suspend.o
|
||||||
|
@ -12,7 +12,6 @@
|
|||||||
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||||
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
|
||||||
|
|
||||||
#include <linux/of.h>
|
|
||||||
#include <linux/platform_data/cpuidle-exynos.h>
|
#include <linux/platform_data/cpuidle-exynos.h>
|
||||||
|
|
||||||
#define EXYNOS3250_SOC_ID 0xE3472000
|
#define EXYNOS3250_SOC_ID 0xE3472000
|
||||||
|
@ -11,29 +11,23 @@
|
|||||||
|
|
||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/serial_s3c.h>
|
|
||||||
#include <linux/of.h>
|
#include <linux/of.h>
|
||||||
#include <linux/of_address.h>
|
#include <linux/of_address.h>
|
||||||
#include <linux/of_fdt.h>
|
#include <linux/of_fdt.h>
|
||||||
#include <linux/of_platform.h>
|
#include <linux/of_platform.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/pm_domain.h>
|
|
||||||
#include <linux/irqchip.h>
|
#include <linux/irqchip.h>
|
||||||
|
#include <linux/soc/samsung/exynos-regs-pmu.h>
|
||||||
|
|
||||||
#include <asm/cacheflush.h>
|
#include <asm/cacheflush.h>
|
||||||
#include <asm/hardware/cache-l2x0.h>
|
#include <asm/hardware/cache-l2x0.h>
|
||||||
#include <asm/mach/arch.h>
|
#include <asm/mach/arch.h>
|
||||||
#include <asm/mach/map.h>
|
#include <asm/mach/map.h>
|
||||||
#include <asm/memory.h>
|
|
||||||
|
|
||||||
#include <mach/map.h>
|
#include <mach/map.h>
|
||||||
|
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
#include "mfc.h"
|
#include "mfc.h"
|
||||||
#include "regs-pmu.h"
|
|
||||||
|
|
||||||
void __iomem *pmu_base_addr;
|
|
||||||
|
|
||||||
static struct map_desc exynos4_iodesc[] __initdata = {
|
static struct map_desc exynos4_iodesc[] __initdata = {
|
||||||
{
|
{
|
||||||
@ -70,11 +64,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
|
|||||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
|
.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
|
||||||
.length = SZ_4K,
|
.length = SZ_4K,
|
||||||
.type = MT_DEVICE,
|
.type = MT_DEVICE,
|
||||||
}, {
|
|
||||||
.virtual = (unsigned long)S5P_VA_CMU,
|
|
||||||
.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
|
|
||||||
.length = 144 * SZ_1K,
|
|
||||||
.type = MT_DEVICE,
|
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -230,6 +219,10 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
|
|||||||
{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
|
{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
|
||||||
{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
|
{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
|
||||||
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
|
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
|
||||||
|
#ifndef CONFIG_BL_SWITCHER
|
||||||
|
{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
|
||||||
|
{ .compatible = "samsung,exynos5800", .data = "cpufreq-dt" },
|
||||||
|
#endif
|
||||||
{ /* sentinel */ }
|
{ /* sentinel */ }
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -20,8 +20,6 @@
|
|||||||
#include <asm/hardware/cache-l2x0.h>
|
#include <asm/hardware/cache-l2x0.h>
|
||||||
#include <asm/suspend.h>
|
#include <asm/suspend.h>
|
||||||
|
|
||||||
#include <mach/map.h>
|
|
||||||
|
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
#include "smc.h"
|
#include "smc.h"
|
||||||
|
|
||||||
|
@ -2,7 +2,7 @@
|
|||||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||||
* http://www.samsung.com/
|
* http://www.samsung.com/
|
||||||
*
|
*
|
||||||
* EXYNOS4 - Memory map definitions
|
* EXYNOS - Memory map definitions
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or modify
|
* This program is free software; you can redistribute it and/or modify
|
||||||
* it under the terms of the GNU General Public License version 2 as
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
@ -14,30 +14,18 @@
|
|||||||
|
|
||||||
#include <plat/map-base.h>
|
#include <plat/map-base.h>
|
||||||
|
|
||||||
/*
|
|
||||||
* EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
|
|
||||||
* So need to define it, and here is to avoid redefinition warning.
|
|
||||||
*/
|
|
||||||
#define S3C_UART_OFFSET (0x10000)
|
|
||||||
|
|
||||||
#include <plat/map-s5p.h>
|
#include <plat/map-s5p.h>
|
||||||
|
|
||||||
#define EXYNOS_PA_CHIPID 0x10000000
|
#define EXYNOS_PA_CHIPID 0x10000000
|
||||||
|
|
||||||
#define EXYNOS4_PA_CMU 0x10030000
|
#define EXYNOS4_PA_CMU 0x10030000
|
||||||
#define EXYNOS5_PA_CMU 0x10010000
|
|
||||||
|
|
||||||
#define EXYNOS4_PA_DMC0 0x10400000
|
#define EXYNOS4_PA_DMC0 0x10400000
|
||||||
#define EXYNOS4_PA_DMC1 0x10410000
|
#define EXYNOS4_PA_DMC1 0x10410000
|
||||||
|
|
||||||
#define EXYNOS4_PA_COREPERI 0x10500000
|
#define EXYNOS4_PA_COREPERI 0x10500000
|
||||||
#define EXYNOS4_PA_L2CC 0x10502000
|
|
||||||
|
|
||||||
#define EXYNOS4_PA_SROMC 0x12570000
|
#define EXYNOS4_PA_SROMC 0x12570000
|
||||||
#define EXYNOS5_PA_SROMC 0x12250000
|
#define EXYNOS5_PA_SROMC 0x12250000
|
||||||
|
|
||||||
/* Compatibility UART */
|
|
||||||
|
|
||||||
#define EXYNOS5440_PA_UART0 0x000B0000
|
|
||||||
|
|
||||||
#endif /* __ASM_ARCH_MAP_H */
|
#endif /* __ASM_ARCH_MAP_H */
|
||||||
|
@ -16,13 +16,13 @@
|
|||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
#include <linux/of_address.h>
|
#include <linux/of_address.h>
|
||||||
#include <linux/syscore_ops.h>
|
#include <linux/syscore_ops.h>
|
||||||
|
#include <linux/soc/samsung/exynos-regs-pmu.h>
|
||||||
|
|
||||||
#include <asm/cputype.h>
|
#include <asm/cputype.h>
|
||||||
#include <asm/cp15.h>
|
#include <asm/cp15.h>
|
||||||
#include <asm/mcpm.h>
|
#include <asm/mcpm.h>
|
||||||
#include <asm/smp_plat.h>
|
#include <asm/smp_plat.h>
|
||||||
|
|
||||||
#include "regs-pmu.h"
|
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
|
|
||||||
#define EXYNOS5420_CPUS_PER_CLUSTER 4
|
#define EXYNOS5420_CPUS_PER_CLUSTER 4
|
||||||
|
@ -15,11 +15,11 @@
|
|||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
#include <linux/errno.h>
|
#include <linux/errno.h>
|
||||||
#include <linux/delay.h>
|
#include <linux/delay.h>
|
||||||
#include <linux/device.h>
|
|
||||||
#include <linux/jiffies.h>
|
#include <linux/jiffies.h>
|
||||||
#include <linux/smp.h>
|
#include <linux/smp.h>
|
||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
#include <linux/of_address.h>
|
#include <linux/of_address.h>
|
||||||
|
#include <linux/soc/samsung/exynos-regs-pmu.h>
|
||||||
|
|
||||||
#include <asm/cacheflush.h>
|
#include <asm/cacheflush.h>
|
||||||
#include <asm/cp15.h>
|
#include <asm/cp15.h>
|
||||||
@ -30,7 +30,6 @@
|
|||||||
#include <mach/map.h>
|
#include <mach/map.h>
|
||||||
|
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
#include "regs-pmu.h"
|
|
||||||
|
|
||||||
extern void exynos4_secondary_startup(void);
|
extern void exynos4_secondary_startup(void);
|
||||||
|
|
||||||
|
@ -17,7 +17,9 @@
|
|||||||
#include <linux/suspend.h>
|
#include <linux/suspend.h>
|
||||||
#include <linux/cpu_pm.h>
|
#include <linux/cpu_pm.h>
|
||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
#include <linux/err.h>
|
#include <linux/of.h>
|
||||||
|
#include <linux/soc/samsung/exynos-regs-pmu.h>
|
||||||
|
#include <linux/soc/samsung/exynos-pmu.h>
|
||||||
|
|
||||||
#include <asm/firmware.h>
|
#include <asm/firmware.h>
|
||||||
#include <asm/smp_scu.h>
|
#include <asm/smp_scu.h>
|
||||||
@ -26,11 +28,7 @@
|
|||||||
|
|
||||||
#include <mach/map.h>
|
#include <mach/map.h>
|
||||||
|
|
||||||
#include <plat/pm-common.h>
|
|
||||||
|
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
#include "exynos-pmu.h"
|
|
||||||
#include "regs-pmu.h"
|
|
||||||
|
|
||||||
static inline void __iomem *exynos_boot_vector_addr(void)
|
static inline void __iomem *exynos_boot_vector_addr(void)
|
||||||
{
|
{
|
||||||
|
@ -1,967 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
|
|
||||||
* http://www.samsung.com/
|
|
||||||
*
|
|
||||||
* EXYNOS - CPU PMU(Power Management Unit) support
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License version 2 as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/io.h>
|
|
||||||
#include <linux/of.h>
|
|
||||||
#include <linux/of_address.h>
|
|
||||||
#include <linux/platform_device.h>
|
|
||||||
#include <linux/delay.h>
|
|
||||||
|
|
||||||
#include <asm/cputype.h>
|
|
||||||
|
|
||||||
#include "exynos-pmu.h"
|
|
||||||
#include "regs-pmu.h"
|
|
||||||
|
|
||||||
#define PMU_TABLE_END (-1U)
|
|
||||||
|
|
||||||
struct exynos_pmu_conf {
|
|
||||||
unsigned int offset;
|
|
||||||
u8 val[NUM_SYS_POWERDOWN];
|
|
||||||
};
|
|
||||||
|
|
||||||
struct exynos_pmu_data {
|
|
||||||
const struct exynos_pmu_conf *pmu_config;
|
|
||||||
const struct exynos_pmu_conf *pmu_config_extra;
|
|
||||||
|
|
||||||
void (*pmu_init)(void);
|
|
||||||
void (*powerdown_conf)(enum sys_powerdown);
|
|
||||||
void (*powerdown_conf_extra)(enum sys_powerdown);
|
|
||||||
};
|
|
||||||
|
|
||||||
struct exynos_pmu_context {
|
|
||||||
struct device *dev;
|
|
||||||
const struct exynos_pmu_data *pmu_data;
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __iomem *pmu_base_addr;
|
|
||||||
static struct exynos_pmu_context *pmu_context;
|
|
||||||
|
|
||||||
static inline void pmu_raw_writel(u32 val, u32 offset)
|
|
||||||
{
|
|
||||||
writel_relaxed(val, pmu_base_addr + offset);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline u32 pmu_raw_readl(u32 offset)
|
|
||||||
{
|
|
||||||
return readl_relaxed(pmu_base_addr + offset);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct exynos_pmu_conf exynos3250_pmu_config[] = {
|
|
||||||
/* { .offset = offset, .val = { AFTR, W-AFTR, SLEEP } */
|
|
||||||
{ EXYNOS3_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
||||||
{ EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
||||||
{ EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
||||||
{ EXYNOS3_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x3} },
|
|
||||||
{ EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS3_TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
|
|
||||||
{ EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
|
|
||||||
{ EXYNOS3_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS3_CAM_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_LCD0_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_MAUDIO_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ PMU_TABLE_END,},
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
|
|
||||||
/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
|
|
||||||
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
||||||
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
||||||
{ S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
||||||
{ S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } },
|
|
||||||
{ S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } },
|
|
||||||
{ S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
||||||
{ S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
|
|
||||||
{ S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
|
|
||||||
{ S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ PMU_TABLE_END,},
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct exynos_pmu_conf exynos4x12_pmu_config[] = {
|
|
||||||
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
||||||
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
||||||
{ S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
||||||
{ S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } },
|
|
||||||
/* XXX_OPTION register should be set other field */
|
|
||||||
{ S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } },
|
|
||||||
{ S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } },
|
|
||||||
{ S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } },
|
|
||||||
{ S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } },
|
|
||||||
{ S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } },
|
|
||||||
{ S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } },
|
|
||||||
{ S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
||||||
{ S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
|
|
||||||
{ S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
||||||
{ S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } },
|
|
||||||
{ S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
||||||
{ S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
||||||
{ S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
||||||
{ S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
||||||
{ S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
||||||
{ S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
||||||
{ S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
||||||
{ S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
||||||
{ S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
||||||
{ S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
|
||||||
{ S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
|
||||||
{ S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } },
|
|
||||||
{ S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } },
|
|
||||||
{ S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
|
|
||||||
{ S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
|
|
||||||
{ PMU_TABLE_END,},
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
|
|
||||||
{ S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
||||||
{ S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } },
|
|
||||||
{ S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } },
|
|
||||||
{ PMU_TABLE_END,},
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
|
|
||||||
/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
|
|
||||||
{ EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
||||||
{ EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
|
|
||||||
{ EXYNOS5_ARM_L2_OPTION, { 0x10, 0x10, 0x0 } },
|
|
||||||
{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
|
||||||
{ EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
|
||||||
{ EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_JPEG_MEM_OPTION, { 0x10, 0x10, 0x0} },
|
|
||||||
{ EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ PMU_TABLE_END,},
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct exynos_pmu_conf exynos5420_pmu_config[] = {
|
|
||||||
/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
|
|
||||||
{ EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_ARM_CORE2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_ARM_CORE3_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_KFC_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_KFC_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_KFC_CORE2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_KFC_CORE3_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_KFC_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_KFC_L2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
||||||
{ EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x0} },
|
|
||||||
{ EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
||||||
{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
|
||||||
{ EXYNOS5420_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
||||||
{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
|
|
||||||
{ EXYNOS5420_G2D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_MSC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_FSYS_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_FSYS2_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_PSGEN_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_PERIC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_WCORE_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
||||||
{ PMU_TABLE_END,},
|
|
||||||
};
|
|
||||||
|
|
||||||
static unsigned int const exynos3250_list_feed[] = {
|
|
||||||
EXYNOS3_ARM_CORE_OPTION(0),
|
|
||||||
EXYNOS3_ARM_CORE_OPTION(1),
|
|
||||||
EXYNOS3_ARM_CORE_OPTION(2),
|
|
||||||
EXYNOS3_ARM_CORE_OPTION(3),
|
|
||||||
EXYNOS3_ARM_COMMON_OPTION,
|
|
||||||
EXYNOS3_TOP_PWR_OPTION,
|
|
||||||
EXYNOS3_CORE_TOP_PWR_OPTION,
|
|
||||||
S5P_CAM_OPTION,
|
|
||||||
S5P_MFC_OPTION,
|
|
||||||
S5P_G3D_OPTION,
|
|
||||||
S5P_LCD0_OPTION,
|
|
||||||
S5P_ISP_OPTION,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void exynos3250_powerdown_conf_extra(enum sys_powerdown mode)
|
|
||||||
{
|
|
||||||
unsigned int i;
|
|
||||||
unsigned int tmp;
|
|
||||||
|
|
||||||
/* Enable only SC_FEEDBACK */
|
|
||||||
for (i = 0; i < ARRAY_SIZE(exynos3250_list_feed); i++) {
|
|
||||||
tmp = pmu_raw_readl(exynos3250_list_feed[i]);
|
|
||||||
tmp &= ~(EXYNOS3_OPTION_USE_SC_COUNTER);
|
|
||||||
tmp |= EXYNOS3_OPTION_USE_SC_FEEDBACK;
|
|
||||||
pmu_raw_writel(tmp, exynos3250_list_feed[i]);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (mode != SYS_SLEEP)
|
|
||||||
return;
|
|
||||||
|
|
||||||
pmu_raw_writel(XUSBXTI_DURATION, EXYNOS3_XUSBXTI_DURATION);
|
|
||||||
pmu_raw_writel(XXTI_DURATION, EXYNOS3_XXTI_DURATION);
|
|
||||||
pmu_raw_writel(EXT_REGULATOR_DURATION, EXYNOS3_EXT_REGULATOR_DURATION);
|
|
||||||
pmu_raw_writel(EXT_REGULATOR_COREBLK_DURATION,
|
|
||||||
EXYNOS3_EXT_REGULATOR_COREBLK_DURATION);
|
|
||||||
}
|
|
||||||
|
|
||||||
static unsigned int const exynos5_list_both_cnt_feed[] = {
|
|
||||||
EXYNOS5_ARM_CORE0_OPTION,
|
|
||||||
EXYNOS5_ARM_CORE1_OPTION,
|
|
||||||
EXYNOS5_ARM_COMMON_OPTION,
|
|
||||||
EXYNOS5_GSCL_OPTION,
|
|
||||||
EXYNOS5_ISP_OPTION,
|
|
||||||
EXYNOS5_MFC_OPTION,
|
|
||||||
EXYNOS5_G3D_OPTION,
|
|
||||||
EXYNOS5_DISP1_OPTION,
|
|
||||||
EXYNOS5_MAU_OPTION,
|
|
||||||
EXYNOS5_TOP_PWR_OPTION,
|
|
||||||
EXYNOS5_TOP_PWR_SYSMEM_OPTION,
|
|
||||||
};
|
|
||||||
|
|
||||||
static unsigned int const exynos5_list_disable_wfi_wfe[] = {
|
|
||||||
EXYNOS5_ARM_CORE1_OPTION,
|
|
||||||
EXYNOS5_FSYS_ARM_OPTION,
|
|
||||||
EXYNOS5_ISP_ARM_OPTION,
|
|
||||||
};
|
|
||||||
|
|
||||||
static unsigned int const exynos5420_list_disable_pmu_reg[] = {
|
|
||||||
EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
|
|
||||||
EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
|
|
||||||
EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,
|
|
||||||
EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
|
|
||||||
EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
|
|
||||||
EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,
|
|
||||||
EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
|
|
||||||
EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,
|
|
||||||
EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,
|
|
||||||
EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void exynos5420_powerdown_conf(enum sys_powerdown mode)
|
|
||||||
{
|
|
||||||
u32 this_cluster;
|
|
||||||
|
|
||||||
this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* set the cluster id to IROM register to ensure that we wake
|
|
||||||
* up with the current cluster.
|
|
||||||
*/
|
|
||||||
pmu_raw_writel(this_cluster, EXYNOS_IROM_DATA2);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
static void exynos5_powerdown_conf(enum sys_powerdown mode)
|
|
||||||
{
|
|
||||||
unsigned int i;
|
|
||||||
unsigned int tmp;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Enable both SC_FEEDBACK and SC_COUNTER
|
|
||||||
*/
|
|
||||||
for (i = 0; i < ARRAY_SIZE(exynos5_list_both_cnt_feed); i++) {
|
|
||||||
tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
|
|
||||||
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
|
|
||||||
EXYNOS5_USE_SC_COUNTER);
|
|
||||||
pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
|
|
||||||
*/
|
|
||||||
tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
|
|
||||||
tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
|
|
||||||
pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Disable WFI/WFE on XXX_OPTION
|
|
||||||
*/
|
|
||||||
for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_wfi_wfe); i++) {
|
|
||||||
tmp = pmu_raw_readl(exynos5_list_disable_wfi_wfe[i]);
|
|
||||||
tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
|
|
||||||
EXYNOS5_OPTION_USE_STANDBYWFI);
|
|
||||||
pmu_raw_writel(tmp, exynos5_list_disable_wfi_wfe[i]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void exynos_sys_powerdown_conf(enum sys_powerdown mode)
|
|
||||||
{
|
|
||||||
unsigned int i;
|
|
||||||
const struct exynos_pmu_data *pmu_data;
|
|
||||||
|
|
||||||
if (!pmu_context)
|
|
||||||
return;
|
|
||||||
|
|
||||||
pmu_data = pmu_context->pmu_data;
|
|
||||||
|
|
||||||
if (pmu_data->powerdown_conf)
|
|
||||||
pmu_data->powerdown_conf(mode);
|
|
||||||
|
|
||||||
if (pmu_data->pmu_config) {
|
|
||||||
for (i = 0; (pmu_data->pmu_config[i].offset != PMU_TABLE_END); i++)
|
|
||||||
pmu_raw_writel(pmu_data->pmu_config[i].val[mode],
|
|
||||||
pmu_data->pmu_config[i].offset);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (pmu_data->powerdown_conf_extra)
|
|
||||||
pmu_data->powerdown_conf_extra(mode);
|
|
||||||
|
|
||||||
if (pmu_data->pmu_config_extra) {
|
|
||||||
for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++)
|
|
||||||
pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
|
|
||||||
pmu_data->pmu_config_extra[i].offset);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void exynos3250_pmu_init(void)
|
|
||||||
{
|
|
||||||
unsigned int value;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* To prevent from issuing new bus request form L2 memory system
|
|
||||||
* If core status is power down, should be set '1' to L2 power down
|
|
||||||
*/
|
|
||||||
value = pmu_raw_readl(EXYNOS3_ARM_COMMON_OPTION);
|
|
||||||
value |= EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
|
|
||||||
pmu_raw_writel(value, EXYNOS3_ARM_COMMON_OPTION);
|
|
||||||
|
|
||||||
/* Enable USE_STANDBY_WFI for all CORE */
|
|
||||||
pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set PSHOLD port for output high
|
|
||||||
*/
|
|
||||||
value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
|
|
||||||
value |= S5P_PS_HOLD_OUTPUT_HIGH;
|
|
||||||
pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Enable signal for PSHOLD port
|
|
||||||
*/
|
|
||||||
value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
|
|
||||||
value |= S5P_PS_HOLD_EN;
|
|
||||||
pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void exynos5250_pmu_init(void)
|
|
||||||
{
|
|
||||||
unsigned int value;
|
|
||||||
/*
|
|
||||||
* When SYS_WDTRESET is set, watchdog timer reset request
|
|
||||||
* is ignored by power management unit.
|
|
||||||
*/
|
|
||||||
value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
|
|
||||||
value &= ~EXYNOS5_SYS_WDTRESET;
|
|
||||||
pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
|
|
||||||
|
|
||||||
value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
|
|
||||||
value &= ~EXYNOS5_SYS_WDTRESET;
|
|
||||||
pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void exynos5420_pmu_init(void)
|
|
||||||
{
|
|
||||||
unsigned int value;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers
|
|
||||||
* for local power blocks to Low initially as per Table 8-4:
|
|
||||||
* "System-Level Power-Down Configuration Registers".
|
|
||||||
*/
|
|
||||||
for (i = 0; i < ARRAY_SIZE(exynos5420_list_disable_pmu_reg); i++)
|
|
||||||
pmu_raw_writel(0, exynos5420_list_disable_pmu_reg[i]);
|
|
||||||
|
|
||||||
/* Enable USE_STANDBY_WFI for all CORE */
|
|
||||||
pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
|
|
||||||
|
|
||||||
value = pmu_raw_readl(EXYNOS_L2_OPTION(0));
|
|
||||||
value &= ~EXYNOS5_USE_RETENTION;
|
|
||||||
pmu_raw_writel(value, EXYNOS_L2_OPTION(0));
|
|
||||||
|
|
||||||
value = pmu_raw_readl(EXYNOS_L2_OPTION(1));
|
|
||||||
value &= ~EXYNOS5_USE_RETENTION;
|
|
||||||
pmu_raw_writel(value, EXYNOS_L2_OPTION(1));
|
|
||||||
|
|
||||||
/*
|
|
||||||
* If L2_COMMON is turned off, clocks related to ATB async
|
|
||||||
* bridge are gated. Thus, when ISP power is gated, LPI
|
|
||||||
* may get stuck.
|
|
||||||
*/
|
|
||||||
value = pmu_raw_readl(EXYNOS5420_LPI_MASK);
|
|
||||||
value |= EXYNOS5420_ATB_ISP_ARM;
|
|
||||||
pmu_raw_writel(value, EXYNOS5420_LPI_MASK);
|
|
||||||
|
|
||||||
value = pmu_raw_readl(EXYNOS5420_LPI_MASK1);
|
|
||||||
value |= EXYNOS5420_ATB_KFC;
|
|
||||||
pmu_raw_writel(value, EXYNOS5420_LPI_MASK1);
|
|
||||||
|
|
||||||
/* Prevent issue of new bus request from L2 memory */
|
|
||||||
value = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
|
|
||||||
value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
|
|
||||||
pmu_raw_writel(value, EXYNOS5420_ARM_COMMON_OPTION);
|
|
||||||
|
|
||||||
value = pmu_raw_readl(EXYNOS5420_KFC_COMMON_OPTION);
|
|
||||||
value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
|
|
||||||
pmu_raw_writel(value, EXYNOS5420_KFC_COMMON_OPTION);
|
|
||||||
|
|
||||||
/* This setting is to reduce suspend/resume time */
|
|
||||||
pmu_raw_writel(DUR_WAIT_RESET, EXYNOS5420_LOGIC_RESET_DURATION3);
|
|
||||||
|
|
||||||
/* Serialized CPU wakeup of Eagle */
|
|
||||||
pmu_raw_writel(SPREAD_ENABLE, EXYNOS5420_ARM_INTR_SPREAD_ENABLE);
|
|
||||||
|
|
||||||
pmu_raw_writel(SPREAD_USE_STANDWFI,
|
|
||||||
EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI);
|
|
||||||
|
|
||||||
pmu_raw_writel(0x1, EXYNOS5420_UP_SCHEDULER);
|
|
||||||
pr_info("EXYNOS5420 PMU initialized\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct exynos_pmu_data exynos3250_pmu_data = {
|
|
||||||
.pmu_config = exynos3250_pmu_config,
|
|
||||||
.pmu_init = exynos3250_pmu_init,
|
|
||||||
.powerdown_conf_extra = exynos3250_powerdown_conf_extra,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct exynos_pmu_data exynos4210_pmu_data = {
|
|
||||||
.pmu_config = exynos4210_pmu_config,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct exynos_pmu_data exynos4212_pmu_data = {
|
|
||||||
.pmu_config = exynos4x12_pmu_config,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct exynos_pmu_data exynos4412_pmu_data = {
|
|
||||||
.pmu_config = exynos4x12_pmu_config,
|
|
||||||
.pmu_config_extra = exynos4412_pmu_config,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct exynos_pmu_data exynos5250_pmu_data = {
|
|
||||||
.pmu_config = exynos5250_pmu_config,
|
|
||||||
.pmu_init = exynos5250_pmu_init,
|
|
||||||
.powerdown_conf = exynos5_powerdown_conf,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct exynos_pmu_data exynos5420_pmu_data = {
|
|
||||||
.pmu_config = exynos5420_pmu_config,
|
|
||||||
.pmu_init = exynos5420_pmu_init,
|
|
||||||
.powerdown_conf = exynos5420_powerdown_conf,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PMU platform driver and devicetree bindings.
|
|
||||||
*/
|
|
||||||
static const struct of_device_id exynos_pmu_of_device_ids[] = {
|
|
||||||
{
|
|
||||||
.compatible = "samsung,exynos3250-pmu",
|
|
||||||
.data = &exynos3250_pmu_data,
|
|
||||||
}, {
|
|
||||||
.compatible = "samsung,exynos4210-pmu",
|
|
||||||
.data = &exynos4210_pmu_data,
|
|
||||||
}, {
|
|
||||||
.compatible = "samsung,exynos4212-pmu",
|
|
||||||
.data = &exynos4212_pmu_data,
|
|
||||||
}, {
|
|
||||||
.compatible = "samsung,exynos4412-pmu",
|
|
||||||
.data = &exynos4412_pmu_data,
|
|
||||||
}, {
|
|
||||||
.compatible = "samsung,exynos5250-pmu",
|
|
||||||
.data = &exynos5250_pmu_data,
|
|
||||||
}, {
|
|
||||||
.compatible = "samsung,exynos5420-pmu",
|
|
||||||
.data = &exynos5420_pmu_data,
|
|
||||||
},
|
|
||||||
{ /*sentinel*/ },
|
|
||||||
};
|
|
||||||
|
|
||||||
static int exynos_pmu_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
const struct of_device_id *match;
|
|
||||||
struct device *dev = &pdev->dev;
|
|
||||||
struct resource *res;
|
|
||||||
|
|
||||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
||||||
pmu_base_addr = devm_ioremap_resource(dev, res);
|
|
||||||
if (IS_ERR(pmu_base_addr))
|
|
||||||
return PTR_ERR(pmu_base_addr);
|
|
||||||
|
|
||||||
pmu_context = devm_kzalloc(&pdev->dev,
|
|
||||||
sizeof(struct exynos_pmu_context),
|
|
||||||
GFP_KERNEL);
|
|
||||||
if (!pmu_context) {
|
|
||||||
dev_err(dev, "Cannot allocate memory.\n");
|
|
||||||
return -ENOMEM;
|
|
||||||
}
|
|
||||||
pmu_context->dev = dev;
|
|
||||||
|
|
||||||
match = of_match_node(exynos_pmu_of_device_ids, dev->of_node);
|
|
||||||
|
|
||||||
pmu_context->pmu_data = match->data;
|
|
||||||
|
|
||||||
if (pmu_context->pmu_data->pmu_init)
|
|
||||||
pmu_context->pmu_data->pmu_init();
|
|
||||||
|
|
||||||
platform_set_drvdata(pdev, pmu_context);
|
|
||||||
|
|
||||||
dev_dbg(dev, "Exynos PMU Driver probe done\n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct platform_driver exynos_pmu_driver = {
|
|
||||||
.driver = {
|
|
||||||
.name = "exynos-pmu",
|
|
||||||
.of_match_table = exynos_pmu_of_device_ids,
|
|
||||||
},
|
|
||||||
.probe = exynos_pmu_probe,
|
|
||||||
};
|
|
||||||
|
|
||||||
static int __init exynos_pmu_init(void)
|
|
||||||
{
|
|
||||||
return platform_driver_register(&exynos_pmu_driver);
|
|
||||||
|
|
||||||
}
|
|
||||||
postcore_initcall(exynos_pmu_init);
|
|
@ -9,7 +9,6 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/kernel.h>
|
#include <linux/kernel.h>
|
||||||
#include <linux/interrupt.h>
|
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/dma-mapping.h>
|
#include <linux/dma-mapping.h>
|
||||||
#include <linux/memblock.h>
|
#include <linux/memblock.h>
|
||||||
|
@ -24,6 +24,8 @@
|
|||||||
#include <linux/of_address.h>
|
#include <linux/of_address.h>
|
||||||
#include <linux/err.h>
|
#include <linux/err.h>
|
||||||
#include <linux/regulator/machine.h>
|
#include <linux/regulator/machine.h>
|
||||||
|
#include <linux/soc/samsung/exynos-pmu.h>
|
||||||
|
#include <linux/soc/samsung/exynos-regs-pmu.h>
|
||||||
|
|
||||||
#include <asm/cacheflush.h>
|
#include <asm/cacheflush.h>
|
||||||
#include <asm/hardware/cache-l2x0.h>
|
#include <asm/hardware/cache-l2x0.h>
|
||||||
@ -35,8 +37,6 @@
|
|||||||
#include <plat/pm-common.h>
|
#include <plat/pm-common.h>
|
||||||
|
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
#include "exynos-pmu.h"
|
|
||||||
#include "regs-pmu.h"
|
|
||||||
#include "regs-srom.h"
|
#include "regs-srom.h"
|
||||||
|
|
||||||
#define REG_TABLE_END (-1U)
|
#define REG_TABLE_END (-1U)
|
||||||
|
@ -94,8 +94,8 @@ static void mxc_expio_irq_handler(struct irq_desc *desc)
|
|||||||
/* irq = gpio irq number */
|
/* irq = gpio irq number */
|
||||||
desc->irq_data.chip->irq_mask(&desc->irq_data);
|
desc->irq_data.chip->irq_mask(&desc->irq_data);
|
||||||
|
|
||||||
imr_val = __raw_readw(brd_io + INTR_MASK_REG);
|
imr_val = imx_readw(brd_io + INTR_MASK_REG);
|
||||||
int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
|
int_valid = imx_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
|
||||||
|
|
||||||
expio_irq = 0;
|
expio_irq = 0;
|
||||||
for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
|
for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
|
||||||
@ -117,17 +117,17 @@ static void expio_mask_irq(struct irq_data *d)
|
|||||||
u16 reg;
|
u16 reg;
|
||||||
u32 expio = d->hwirq;
|
u32 expio = d->hwirq;
|
||||||
|
|
||||||
reg = __raw_readw(brd_io + INTR_MASK_REG);
|
reg = imx_readw(brd_io + INTR_MASK_REG);
|
||||||
reg |= (1 << expio);
|
reg |= (1 << expio);
|
||||||
__raw_writew(reg, brd_io + INTR_MASK_REG);
|
imx_writew(reg, brd_io + INTR_MASK_REG);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void expio_ack_irq(struct irq_data *d)
|
static void expio_ack_irq(struct irq_data *d)
|
||||||
{
|
{
|
||||||
u32 expio = d->hwirq;
|
u32 expio = d->hwirq;
|
||||||
|
|
||||||
__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
|
imx_writew(1 << expio, brd_io + INTR_RESET_REG);
|
||||||
__raw_writew(0, brd_io + INTR_RESET_REG);
|
imx_writew(0, brd_io + INTR_RESET_REG);
|
||||||
expio_mask_irq(d);
|
expio_mask_irq(d);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -136,9 +136,9 @@ static void expio_unmask_irq(struct irq_data *d)
|
|||||||
u16 reg;
|
u16 reg;
|
||||||
u32 expio = d->hwirq;
|
u32 expio = d->hwirq;
|
||||||
|
|
||||||
reg = __raw_readw(brd_io + INTR_MASK_REG);
|
reg = imx_readw(brd_io + INTR_MASK_REG);
|
||||||
reg &= ~(1 << expio);
|
reg &= ~(1 << expio);
|
||||||
__raw_writew(reg, brd_io + INTR_MASK_REG);
|
imx_writew(reg, brd_io + INTR_MASK_REG);
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_chip expio_irq_chip = {
|
static struct irq_chip expio_irq_chip = {
|
||||||
@ -162,9 +162,9 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio)
|
|||||||
if (brd_io == NULL)
|
if (brd_io == NULL)
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
|
||||||
if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
|
if ((imx_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
|
||||||
(__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
|
(imx_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
|
||||||
(__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
|
(imx_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
|
||||||
pr_info("3-Stack Debug board not detected\n");
|
pr_info("3-Stack Debug board not detected\n");
|
||||||
iounmap(brd_io);
|
iounmap(brd_io);
|
||||||
brd_io = NULL;
|
brd_io = NULL;
|
||||||
@ -181,10 +181,10 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio)
|
|||||||
gpio_direction_input(intr_gpio);
|
gpio_direction_input(intr_gpio);
|
||||||
|
|
||||||
/* disable the interrupt and clear the status */
|
/* disable the interrupt and clear the status */
|
||||||
__raw_writew(0, brd_io + INTR_MASK_REG);
|
imx_writew(0, brd_io + INTR_MASK_REG);
|
||||||
__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
|
imx_writew(0xFFFF, brd_io + INTR_RESET_REG);
|
||||||
__raw_writew(0, brd_io + INTR_RESET_REG);
|
imx_writew(0, brd_io + INTR_RESET_REG);
|
||||||
__raw_writew(0x1F, brd_io + INTR_MASK_REG);
|
imx_writew(0x1F, brd_io + INTR_MASK_REG);
|
||||||
|
|
||||||
irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
|
irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
|
||||||
WARN_ON(irq_base < 0);
|
WARN_ON(irq_base < 0);
|
||||||
|
@ -2,7 +2,7 @@ menuconfig ARCH_MXC
|
|||||||
bool "Freescale i.MX family"
|
bool "Freescale i.MX family"
|
||||||
depends on ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
|
depends on ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
|
||||||
select ARCH_REQUIRE_GPIOLIB
|
select ARCH_REQUIRE_GPIOLIB
|
||||||
select ARM_CPU_SUSPEND if PM
|
select ARCH_SUPPORTS_BIG_ENDIAN
|
||||||
select CLKSRC_IMX_GPT
|
select CLKSRC_IMX_GPT
|
||||||
select GENERIC_IRQ_CHIP
|
select GENERIC_IRQ_CHIP
|
||||||
select PINCTRL
|
select PINCTRL
|
||||||
@ -511,6 +511,7 @@ config SOC_IMX53
|
|||||||
|
|
||||||
config SOC_IMX6
|
config SOC_IMX6
|
||||||
bool
|
bool
|
||||||
|
select ARM_CPU_SUSPEND if PM
|
||||||
select ARM_ERRATA_754322
|
select ARM_ERRATA_754322
|
||||||
select ARM_ERRATA_775420
|
select ARM_ERRATA_775420
|
||||||
select ARM_GIC
|
select ARM_GIC
|
||||||
@ -561,6 +562,7 @@ config SOC_IMX7D
|
|||||||
bool "i.MX7 Dual support"
|
bool "i.MX7 Dual support"
|
||||||
select PINCTRL_IMX7D
|
select PINCTRL_IMX7D
|
||||||
select ARM_GIC
|
select ARM_GIC
|
||||||
|
select HAVE_ARM_ARCH_TIMER
|
||||||
select HAVE_IMX_ANATOP
|
select HAVE_IMX_ANATOP
|
||||||
select HAVE_IMX_MMDC
|
select HAVE_IMX_MMDC
|
||||||
select HAVE_IMX_SRC
|
select HAVE_IMX_SRC
|
||||||
|
@ -3,7 +3,7 @@ obj-y := cpu.o system.o irq-common.o
|
|||||||
obj-$(CONFIG_SOC_IMX1) += mm-imx1.o
|
obj-$(CONFIG_SOC_IMX1) += mm-imx1.o
|
||||||
obj-$(CONFIG_SOC_IMX21) += mm-imx21.o
|
obj-$(CONFIG_SOC_IMX21) += mm-imx21.o
|
||||||
|
|
||||||
obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o
|
obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
|
||||||
|
|
||||||
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
|
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
|
||||||
obj-$(CONFIG_SOC_IMX27) += mm-imx27.o ehci-imx27.o
|
obj-$(CONFIG_SOC_IMX27) += mm-imx27.o ehci-imx27.o
|
||||||
|
@ -129,7 +129,14 @@ void __init imx_init_revision_from_anatop(void)
|
|||||||
|
|
||||||
switch (digprog & 0xff) {
|
switch (digprog & 0xff) {
|
||||||
case 0:
|
case 0:
|
||||||
revision = IMX_CHIP_REVISION_1_0;
|
/*
|
||||||
|
* For i.MX6QP, most of the code for i.MX6Q can be resued,
|
||||||
|
* so internally, we identify it as i.MX6Q Rev 2.0
|
||||||
|
*/
|
||||||
|
if (digprog >> 8 & 0x01)
|
||||||
|
revision = IMX_CHIP_REVISION_2_0;
|
||||||
|
else
|
||||||
|
revision = IMX_CHIP_REVISION_1_0;
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
revision = IMX_CHIP_REVISION_1_1;
|
revision = IMX_CHIP_REVISION_1_1;
|
||||||
@ -151,7 +158,14 @@ void __init imx_init_revision_from_anatop(void)
|
|||||||
revision = IMX_CHIP_REVISION_1_5;
|
revision = IMX_CHIP_REVISION_1_5;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
revision = IMX_CHIP_REVISION_UNKNOWN;
|
/*
|
||||||
|
* Fail back to return raw register value instead of 0xff.
|
||||||
|
* It will be easy to know version information in SOC if it
|
||||||
|
* can't be recognized by known version. And some chip's (i.MX7D)
|
||||||
|
* digprog value match linux version format, so it needn't map
|
||||||
|
* again and we can use register value directly.
|
||||||
|
*/
|
||||||
|
revision = digprog & 0xff;
|
||||||
}
|
}
|
||||||
|
|
||||||
mxc_set_cpu_type(digprog >> 16 & 0xff);
|
mxc_set_cpu_type(digprog >> 16 & 0xff);
|
||||||
|
@ -66,12 +66,12 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
|
|||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
if (irq < AVIC_NUM_IRQS / 2) {
|
if (irq < AVIC_NUM_IRQS / 2) {
|
||||||
irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
|
irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
|
||||||
__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
|
imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
|
||||||
} else {
|
} else {
|
||||||
irq -= AVIC_NUM_IRQS / 2;
|
irq -= AVIC_NUM_IRQS / 2;
|
||||||
irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
|
irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
|
||||||
__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
|
imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
@ -94,8 +94,8 @@ static void avic_irq_suspend(struct irq_data *d)
|
|||||||
struct irq_chip_type *ct = gc->chip_types;
|
struct irq_chip_type *ct = gc->chip_types;
|
||||||
int idx = d->hwirq >> 5;
|
int idx = d->hwirq >> 5;
|
||||||
|
|
||||||
avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
|
avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
|
||||||
__raw_writel(gc->wake_active, avic_base + ct->regs.mask);
|
imx_writel(gc->wake_active, avic_base + ct->regs.mask);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void avic_irq_resume(struct irq_data *d)
|
static void avic_irq_resume(struct irq_data *d)
|
||||||
@ -104,7 +104,7 @@ static void avic_irq_resume(struct irq_data *d)
|
|||||||
struct irq_chip_type *ct = gc->chip_types;
|
struct irq_chip_type *ct = gc->chip_types;
|
||||||
int idx = d->hwirq >> 5;
|
int idx = d->hwirq >> 5;
|
||||||
|
|
||||||
__raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
|
imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
|
||||||
}
|
}
|
||||||
|
|
||||||
#else
|
#else
|
||||||
@ -140,7 +140,7 @@ static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
|
|||||||
u32 nivector;
|
u32 nivector;
|
||||||
|
|
||||||
do {
|
do {
|
||||||
nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
|
nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;
|
||||||
if (nivector == 0xffff)
|
if (nivector == 0xffff)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
@ -164,16 +164,16 @@ void __init mxc_init_irq(void __iomem *irqbase)
|
|||||||
/* put the AVIC into the reset value with
|
/* put the AVIC into the reset value with
|
||||||
* all interrupts disabled
|
* all interrupts disabled
|
||||||
*/
|
*/
|
||||||
__raw_writel(0, avic_base + AVIC_INTCNTL);
|
imx_writel(0, avic_base + AVIC_INTCNTL);
|
||||||
__raw_writel(0x1f, avic_base + AVIC_NIMASK);
|
imx_writel(0x1f, avic_base + AVIC_NIMASK);
|
||||||
|
|
||||||
/* disable all interrupts */
|
/* disable all interrupts */
|
||||||
__raw_writel(0, avic_base + AVIC_INTENABLEH);
|
imx_writel(0, avic_base + AVIC_INTENABLEH);
|
||||||
__raw_writel(0, avic_base + AVIC_INTENABLEL);
|
imx_writel(0, avic_base + AVIC_INTENABLEL);
|
||||||
|
|
||||||
/* all IRQ no FIQ */
|
/* all IRQ no FIQ */
|
||||||
__raw_writel(0, avic_base + AVIC_INTTYPEH);
|
imx_writel(0, avic_base + AVIC_INTTYPEH);
|
||||||
__raw_writel(0, avic_base + AVIC_INTTYPEL);
|
imx_writel(0, avic_base + AVIC_INTTYPEL);
|
||||||
|
|
||||||
irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
|
irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
|
||||||
WARN_ON(irq_base < 0);
|
WARN_ON(irq_base < 0);
|
||||||
@ -188,7 +188,7 @@ void __init mxc_init_irq(void __iomem *irqbase)
|
|||||||
|
|
||||||
/* Set default priority value (0) for all IRQ's */
|
/* Set default priority value (0) for all IRQ's */
|
||||||
for (i = 0; i < 8; i++)
|
for (i = 0; i < 8; i++)
|
||||||
__raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
|
imx_writel(0, avic_base + AVIC_NIPRIORITY(i));
|
||||||
|
|
||||||
set_handle_irq(avic_handle_irq);
|
set_handle_irq(avic_handle_irq);
|
||||||
|
|
||||||
|
@ -66,6 +66,7 @@ void imx_gpc_check_dt(void);
|
|||||||
void imx_gpc_set_arm_power_in_lpm(bool power_off);
|
void imx_gpc_set_arm_power_in_lpm(bool power_off);
|
||||||
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
|
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
|
||||||
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
|
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
|
||||||
|
void imx25_pm_init(void);
|
||||||
|
|
||||||
enum mxc_cpu_pwr_mode {
|
enum mxc_cpu_pwr_mode {
|
||||||
WAIT_CLOCKED, /* wfi only */
|
WAIT_CLOCKED, /* wfi only */
|
||||||
|
@ -39,8 +39,7 @@ static int mx27_read_cpu_rev(void)
|
|||||||
* the silicon revision very early we read it here to
|
* the silicon revision very early we read it here to
|
||||||
* avoid any further hooks
|
* avoid any further hooks
|
||||||
*/
|
*/
|
||||||
val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
|
val = imx_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID));
|
||||||
+ SYS_CHIP_ID));
|
|
||||||
|
|
||||||
mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF);
|
mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF);
|
||||||
|
|
||||||
|
@ -39,7 +39,7 @@ static int mx31_read_cpu_rev(void)
|
|||||||
u32 i, srev;
|
u32 i, srev;
|
||||||
|
|
||||||
/* read SREV register from IIM module */
|
/* read SREV register from IIM module */
|
||||||
srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
|
srev = imx_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
|
||||||
srev &= 0xff;
|
srev &= 0xff;
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
|
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
|
||||||
|
@ -20,7 +20,7 @@ static int mx35_read_cpu_rev(void)
|
|||||||
{
|
{
|
||||||
u32 rev;
|
u32 rev;
|
||||||
|
|
||||||
rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
|
rev = imx_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
|
||||||
switch (rev) {
|
switch (rev) {
|
||||||
case 0x00:
|
case 0x00:
|
||||||
return IMX_CHIP_REVISION_1_0;
|
return IMX_CHIP_REVISION_1_0;
|
||||||
|
@ -45,20 +45,20 @@ void __init imx_set_aips(void __iomem *base)
|
|||||||
* Set all MPROTx to be non-bufferable, trusted for R/W,
|
* Set all MPROTx to be non-bufferable, trusted for R/W,
|
||||||
* not forced to user-mode.
|
* not forced to user-mode.
|
||||||
*/
|
*/
|
||||||
__raw_writel(0x77777777, base + 0x0);
|
imx_writel(0x77777777, base + 0x0);
|
||||||
__raw_writel(0x77777777, base + 0x4);
|
imx_writel(0x77777777, base + 0x4);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Set all OPACRx to be non-bufferable, to not require
|
* Set all OPACRx to be non-bufferable, to not require
|
||||||
* supervisor privilege level for access, allow for
|
* supervisor privilege level for access, allow for
|
||||||
* write access and untrusted master access.
|
* write access and untrusted master access.
|
||||||
*/
|
*/
|
||||||
__raw_writel(0x0, base + 0x40);
|
imx_writel(0x0, base + 0x40);
|
||||||
__raw_writel(0x0, base + 0x44);
|
imx_writel(0x0, base + 0x44);
|
||||||
__raw_writel(0x0, base + 0x48);
|
imx_writel(0x0, base + 0x48);
|
||||||
__raw_writel(0x0, base + 0x4C);
|
imx_writel(0x0, base + 0x4C);
|
||||||
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
|
reg = imx_readl(base + 0x50) & 0x00FFFFFF;
|
||||||
__raw_writel(reg, base + 0x50);
|
imx_writel(reg, base + 0x50);
|
||||||
}
|
}
|
||||||
|
|
||||||
void __init imx_aips_allow_unprivileged_access(
|
void __init imx_aips_allow_unprivileged_access(
|
||||||
|
@ -64,23 +64,23 @@ static inline void epit_irq_disable(void)
|
|||||||
{
|
{
|
||||||
u32 val;
|
u32 val;
|
||||||
|
|
||||||
val = __raw_readl(timer_base + EPITCR);
|
val = imx_readl(timer_base + EPITCR);
|
||||||
val &= ~EPITCR_OCIEN;
|
val &= ~EPITCR_OCIEN;
|
||||||
__raw_writel(val, timer_base + EPITCR);
|
imx_writel(val, timer_base + EPITCR);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void epit_irq_enable(void)
|
static inline void epit_irq_enable(void)
|
||||||
{
|
{
|
||||||
u32 val;
|
u32 val;
|
||||||
|
|
||||||
val = __raw_readl(timer_base + EPITCR);
|
val = imx_readl(timer_base + EPITCR);
|
||||||
val |= EPITCR_OCIEN;
|
val |= EPITCR_OCIEN;
|
||||||
__raw_writel(val, timer_base + EPITCR);
|
imx_writel(val, timer_base + EPITCR);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void epit_irq_acknowledge(void)
|
static void epit_irq_acknowledge(void)
|
||||||
{
|
{
|
||||||
__raw_writel(EPITSR_OCIF, timer_base + EPITSR);
|
imx_writel(EPITSR_OCIF, timer_base + EPITSR);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int __init epit_clocksource_init(struct clk *timer_clk)
|
static int __init epit_clocksource_init(struct clk *timer_clk)
|
||||||
@ -98,9 +98,9 @@ static int epit_set_next_event(unsigned long evt,
|
|||||||
{
|
{
|
||||||
unsigned long tcmp;
|
unsigned long tcmp;
|
||||||
|
|
||||||
tcmp = __raw_readl(timer_base + EPITCNR);
|
tcmp = imx_readl(timer_base + EPITCNR);
|
||||||
|
|
||||||
__raw_writel(tcmp - evt, timer_base + EPITCMPR);
|
imx_writel(tcmp - evt, timer_base + EPITCMPR);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
@ -213,11 +213,11 @@ void __init epit_timer_init(void __iomem *base, int irq)
|
|||||||
/*
|
/*
|
||||||
* Initialise to a known state (all timers off, and timing reset)
|
* Initialise to a known state (all timers off, and timing reset)
|
||||||
*/
|
*/
|
||||||
__raw_writel(0x0, timer_base + EPITCR);
|
imx_writel(0x0, timer_base + EPITCR);
|
||||||
|
|
||||||
__raw_writel(0xffffffff, timer_base + EPITLR);
|
imx_writel(0xffffffff, timer_base + EPITLR);
|
||||||
__raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
|
imx_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
|
||||||
timer_base + EPITCR);
|
timer_base + EPITCR);
|
||||||
|
|
||||||
/* init and register the timer to the framework */
|
/* init and register the timer to the framework */
|
||||||
epit_clocksource_init(timer_clk);
|
epit_clocksource_init(timer_clk);
|
||||||
|
@ -12,6 +12,7 @@
|
|||||||
|
|
||||||
#include <linux/linkage.h>
|
#include <linux/linkage.h>
|
||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
|
#include <asm/assembler.h>
|
||||||
|
|
||||||
diag_reg_offset:
|
diag_reg_offset:
|
||||||
.word g_diag_reg - .
|
.word g_diag_reg - .
|
||||||
@ -25,6 +26,7 @@ diag_reg_offset:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
ENTRY(v7_secondary_startup)
|
ENTRY(v7_secondary_startup)
|
||||||
|
ARM_BE8(setend be) @ go BE8 if entered LE
|
||||||
set_diag_reg
|
set_diag_reg
|
||||||
b secondary_startup
|
b secondary_startup
|
||||||
ENDPROC(v7_secondary_startup)
|
ENDPROC(v7_secondary_startup)
|
||||||
|
@ -57,10 +57,10 @@ void mxc_iomux_mode(unsigned int pin_mode)
|
|||||||
|
|
||||||
spin_lock(&gpio_mux_lock);
|
spin_lock(&gpio_mux_lock);
|
||||||
|
|
||||||
l = __raw_readl(reg);
|
l = imx_readl(reg);
|
||||||
l &= ~(0xff << (field * 8));
|
l &= ~(0xff << (field * 8));
|
||||||
l |= mode << (field * 8);
|
l |= mode << (field * 8);
|
||||||
__raw_writel(l, reg);
|
imx_writel(l, reg);
|
||||||
|
|
||||||
spin_unlock(&gpio_mux_lock);
|
spin_unlock(&gpio_mux_lock);
|
||||||
}
|
}
|
||||||
@ -82,10 +82,10 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
|
|||||||
|
|
||||||
spin_lock(&gpio_mux_lock);
|
spin_lock(&gpio_mux_lock);
|
||||||
|
|
||||||
l = __raw_readl(reg);
|
l = imx_readl(reg);
|
||||||
l &= ~(0x1ff << (field * 10));
|
l &= ~(0x1ff << (field * 10));
|
||||||
l |= config << (field * 10);
|
l |= config << (field * 10);
|
||||||
__raw_writel(l, reg);
|
imx_writel(l, reg);
|
||||||
|
|
||||||
spin_unlock(&gpio_mux_lock);
|
spin_unlock(&gpio_mux_lock);
|
||||||
}
|
}
|
||||||
@ -163,12 +163,12 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
|
|||||||
u32 l;
|
u32 l;
|
||||||
|
|
||||||
spin_lock(&gpio_mux_lock);
|
spin_lock(&gpio_mux_lock);
|
||||||
l = __raw_readl(IOMUXGPR);
|
l = imx_readl(IOMUXGPR);
|
||||||
if (en)
|
if (en)
|
||||||
l |= gp;
|
l |= gp;
|
||||||
else
|
else
|
||||||
l &= ~gp;
|
l &= ~gp;
|
||||||
|
|
||||||
__raw_writel(l, IOMUXGPR);
|
imx_writel(l, IOMUXGPR);
|
||||||
spin_unlock(&gpio_mux_lock);
|
spin_unlock(&gpio_mux_lock);
|
||||||
}
|
}
|
||||||
|
@ -38,12 +38,12 @@ static unsigned imx_iomuxv1_numports;
|
|||||||
|
|
||||||
static inline unsigned long imx_iomuxv1_readl(unsigned offset)
|
static inline unsigned long imx_iomuxv1_readl(unsigned offset)
|
||||||
{
|
{
|
||||||
return __raw_readl(imx_iomuxv1_baseaddr + offset);
|
return imx_readl(imx_iomuxv1_baseaddr + offset);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset)
|
static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset)
|
||||||
{
|
{
|
||||||
__raw_writel(val, imx_iomuxv1_baseaddr + offset);
|
imx_writel(val, imx_iomuxv1_baseaddr + offset);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void imx_iomuxv1_rmwl(unsigned offset,
|
static inline void imx_iomuxv1_rmwl(unsigned offset,
|
||||||
|
@ -45,13 +45,13 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
|
|||||||
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
|
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
|
||||||
|
|
||||||
if (mux_ctrl_ofs)
|
if (mux_ctrl_ofs)
|
||||||
__raw_writel(mux_mode, base + mux_ctrl_ofs);
|
imx_writel(mux_mode, base + mux_ctrl_ofs);
|
||||||
|
|
||||||
if (sel_input_ofs)
|
if (sel_input_ofs)
|
||||||
__raw_writel(sel_input, base + sel_input_ofs);
|
imx_writel(sel_input, base + sel_input_ofs);
|
||||||
|
|
||||||
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
|
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
|
||||||
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
|
imx_writel(pad_ctrl, base + pad_ctrl_ofs);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -525,8 +525,8 @@ static void __init armadillo5x0_init(void)
|
|||||||
imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
|
imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
|
||||||
|
|
||||||
/* set NAND page size to 2k if not configured via boot mode pins */
|
/* set NAND page size to 2k if not configured via boot mode pins */
|
||||||
__raw_writel(__raw_readl(mx3_ccm_base + MXC_CCM_RCSR) |
|
imx_writel(imx_readl(mx3_ccm_base + MXC_CCM_RCSR) | (1 << 30),
|
||||||
(1 << 30), mx3_ccm_base + MXC_CCM_RCSR);
|
mx3_ccm_base + MXC_CCM_RCSR);
|
||||||
|
|
||||||
/* RTC */
|
/* RTC */
|
||||||
/* Get RTC IRQ and register the chip */
|
/* Get RTC IRQ and register the chip */
|
||||||
|
@ -41,6 +41,7 @@ static const char * const imx25_dt_board_compat[] __initconst = {
|
|||||||
|
|
||||||
DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
|
DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
|
||||||
.init_early = imx25_init_early,
|
.init_early = imx25_init_early,
|
||||||
|
.init_late = imx25_pm_init,
|
||||||
.init_irq = mx25_init_irq,
|
.init_irq = mx25_init_irq,
|
||||||
.dt_compat = imx25_dt_board_compat,
|
.dt_compat = imx25_dt_board_compat,
|
||||||
MACHINE_END
|
MACHINE_END
|
||||||
|
@ -40,11 +40,10 @@ static void __init imx51_ipu_mipi_setup(void)
|
|||||||
WARN_ON(!hsc_addr);
|
WARN_ON(!hsc_addr);
|
||||||
|
|
||||||
/* setup MIPI module to legacy mode */
|
/* setup MIPI module to legacy mode */
|
||||||
__raw_writel(0xf00, hsc_addr);
|
imx_writel(0xf00, hsc_addr);
|
||||||
|
|
||||||
/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
|
/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
|
||||||
__raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
|
imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800);
|
||||||
hsc_addr + 0x800);
|
|
||||||
|
|
||||||
iounmap(hsc_addr);
|
iounmap(hsc_addr);
|
||||||
}
|
}
|
||||||
|
@ -266,8 +266,11 @@ static void __init imx6q_init_machine(void)
|
|||||||
{
|
{
|
||||||
struct device *parent;
|
struct device *parent;
|
||||||
|
|
||||||
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
|
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
|
||||||
imx_get_soc_revision());
|
imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
|
||||||
|
else
|
||||||
|
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
|
||||||
|
imx_get_soc_revision());
|
||||||
|
|
||||||
parent = imx_soc_device_init();
|
parent = imx_soc_device_init();
|
||||||
if (parent == NULL)
|
if (parent == NULL)
|
||||||
@ -399,6 +402,7 @@ static void __init imx6q_init_irq(void)
|
|||||||
static const char * const imx6q_dt_compat[] __initconst = {
|
static const char * const imx6q_dt_compat[] __initconst = {
|
||||||
"fsl,imx6dl",
|
"fsl,imx6dl",
|
||||||
"fsl,imx6q",
|
"fsl,imx6q",
|
||||||
|
"fsl,imx6qp",
|
||||||
NULL,
|
NULL,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -204,9 +204,9 @@ static struct i2c_board_info mx27ads_i2c_devices[] = {
|
|||||||
static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||||
{
|
{
|
||||||
if (value)
|
if (value)
|
||||||
__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
|
imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
|
||||||
else
|
else
|
||||||
__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
|
imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
|
static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
|
||||||
@ -366,7 +366,7 @@ static void __init mx27ads_timer_init(void)
|
|||||||
{
|
{
|
||||||
unsigned long fref = 26000000;
|
unsigned long fref = 26000000;
|
||||||
|
|
||||||
if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
|
if ((imx_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
|
||||||
fref = 27000000;
|
fref = 27000000;
|
||||||
|
|
||||||
mx27_clocks_init(fref);
|
mx27_clocks_init(fref);
|
||||||
|
@ -160,8 +160,8 @@ static void mx31ads_expio_irq_handler(struct irq_desc *desc)
|
|||||||
u32 int_valid;
|
u32 int_valid;
|
||||||
u32 expio_irq;
|
u32 expio_irq;
|
||||||
|
|
||||||
imr_val = __raw_readw(PBC_INTMASK_SET_REG);
|
imr_val = imx_readw(PBC_INTMASK_SET_REG);
|
||||||
int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
|
int_valid = imx_readw(PBC_INTSTATUS_REG) & imr_val;
|
||||||
|
|
||||||
expio_irq = 0;
|
expio_irq = 0;
|
||||||
for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
|
for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
|
||||||
@ -180,8 +180,8 @@ static void expio_mask_irq(struct irq_data *d)
|
|||||||
{
|
{
|
||||||
u32 expio = d->hwirq;
|
u32 expio = d->hwirq;
|
||||||
/* mask the interrupt */
|
/* mask the interrupt */
|
||||||
__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
|
imx_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
|
||||||
__raw_readw(PBC_INTMASK_CLEAR_REG);
|
imx_readw(PBC_INTMASK_CLEAR_REG);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -192,7 +192,7 @@ static void expio_ack_irq(struct irq_data *d)
|
|||||||
{
|
{
|
||||||
u32 expio = d->hwirq;
|
u32 expio = d->hwirq;
|
||||||
/* clear the interrupt status */
|
/* clear the interrupt status */
|
||||||
__raw_writew(1 << expio, PBC_INTSTATUS_REG);
|
imx_writew(1 << expio, PBC_INTSTATUS_REG);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -203,7 +203,7 @@ static void expio_unmask_irq(struct irq_data *d)
|
|||||||
{
|
{
|
||||||
u32 expio = d->hwirq;
|
u32 expio = d->hwirq;
|
||||||
/* unmask the interrupt */
|
/* unmask the interrupt */
|
||||||
__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
|
imx_writew(1 << expio, PBC_INTMASK_SET_REG);
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_chip expio_irq_chip = {
|
static struct irq_chip expio_irq_chip = {
|
||||||
@ -226,8 +226,8 @@ static void __init mx31ads_init_expio(void)
|
|||||||
mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
|
mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
|
||||||
|
|
||||||
/* disable the interrupt and clear the status */
|
/* disable the interrupt and clear the status */
|
||||||
__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
|
imx_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
|
||||||
__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
|
imx_writew(0xFFFF, PBC_INTSTATUS_REG);
|
||||||
|
|
||||||
irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
|
irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
|
||||||
WARN_ON(irq_base < 0);
|
WARN_ON(irq_base < 0);
|
||||||
|
@ -509,7 +509,7 @@ static void mx31moboard_poweroff(void)
|
|||||||
|
|
||||||
mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST);
|
mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST);
|
||||||
|
|
||||||
__raw_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
|
imx_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
|
||||||
}
|
}
|
||||||
|
|
||||||
static int mx31moboard_baseboard;
|
static int mx31moboard_baseboard;
|
||||||
|
@ -190,9 +190,9 @@ static struct platform_device qong_nand_device = {
|
|||||||
static void __init qong_init_nand_mtd(void)
|
static void __init qong_init_nand_mtd(void)
|
||||||
{
|
{
|
||||||
/* init CS */
|
/* init CS */
|
||||||
__raw_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3)));
|
imx_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3)));
|
||||||
__raw_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3)));
|
imx_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3)));
|
||||||
__raw_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3)));
|
imx_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3)));
|
||||||
|
|
||||||
mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
|
mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
|
||||||
|
|
||||||
|
@ -193,4 +193,9 @@ extern struct cpu_op *(*get_cpu_op)(int *op);
|
|||||||
#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
|
#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
|
||||||
#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
|
#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
|
||||||
|
|
||||||
|
#define imx_readl readl_relaxed
|
||||||
|
#define imx_readw readw_relaxed
|
||||||
|
#define imx_writel writel_relaxed
|
||||||
|
#define imx_writew writew_relaxed
|
||||||
|
|
||||||
#endif /* __ASM_ARCH_MXC_H__ */
|
#endif /* __ASM_ARCH_MXC_H__ */
|
||||||
|
37
arch/arm/mach-imx/pm-imx25.c
Normal file
37
arch/arm/mach-imx/pm-imx25.c
Normal file
@ -0,0 +1,37 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2016 NXP Semiconductors
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/suspend.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
|
||||||
|
static int imx25_suspend_enter(suspend_state_t state)
|
||||||
|
{
|
||||||
|
if (!IS_ENABLED(CONFIG_PM))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
switch (state) {
|
||||||
|
case PM_SUSPEND_MEM:
|
||||||
|
cpu_do_idle();
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct platform_suspend_ops imx25_suspend_ops = {
|
||||||
|
.enter = imx25_suspend_enter,
|
||||||
|
.valid = suspend_valid_only_mem,
|
||||||
|
};
|
||||||
|
|
||||||
|
void __init imx25_pm_init(void)
|
||||||
|
{
|
||||||
|
suspend_set_ops(&imx25_suspend_ops);
|
||||||
|
}
|
@ -19,9 +19,9 @@ static int mx27_suspend_enter(suspend_state_t state)
|
|||||||
switch (state) {
|
switch (state) {
|
||||||
case PM_SUSPEND_MEM:
|
case PM_SUSPEND_MEM:
|
||||||
/* Clear MPEN and SPEN to disable MPLL/SPLL */
|
/* Clear MPEN and SPEN to disable MPLL/SPLL */
|
||||||
cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
|
cscr = imx_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
|
||||||
cscr &= 0xFFFFFFFC;
|
cscr &= 0xFFFFFFFC;
|
||||||
__raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
|
imx_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
|
||||||
/* Executes WFI */
|
/* Executes WFI */
|
||||||
cpu_do_idle();
|
cpu_do_idle();
|
||||||
break;
|
break;
|
||||||
|
@ -22,14 +22,14 @@
|
|||||||
*/
|
*/
|
||||||
void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
|
void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
|
||||||
{
|
{
|
||||||
int reg = __raw_readl(mx3_ccm_base + MXC_CCM_CCMR);
|
int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
|
||||||
reg &= ~MXC_CCM_CCMR_LPM_MASK;
|
reg &= ~MXC_CCM_CCMR_LPM_MASK;
|
||||||
|
|
||||||
switch (mode) {
|
switch (mode) {
|
||||||
case MX3_WAIT:
|
case MX3_WAIT:
|
||||||
if (cpu_is_mx35())
|
if (cpu_is_mx35())
|
||||||
reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
|
reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
|
||||||
__raw_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
|
imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
pr_err("Unknown cpu power mode: %d\n", mode);
|
pr_err("Unknown cpu power mode: %d\n", mode);
|
||||||
|
@ -153,15 +153,15 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
|
|||||||
int stop_mode = 0;
|
int stop_mode = 0;
|
||||||
|
|
||||||
/* always allow platform to issue a deep sleep mode request */
|
/* always allow platform to issue a deep sleep mode request */
|
||||||
plat_lpc = __raw_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) &
|
plat_lpc = imx_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) &
|
||||||
~(MXC_CORTEXA8_PLAT_LPC_DSM);
|
~(MXC_CORTEXA8_PLAT_LPC_DSM);
|
||||||
ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) &
|
ccm_clpcr = imx_readl(ccm_base + MXC_CCM_CLPCR) &
|
||||||
~(MXC_CCM_CLPCR_LPM_MASK);
|
~(MXC_CCM_CLPCR_LPM_MASK);
|
||||||
arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) &
|
arm_srpgcr = imx_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) &
|
||||||
~(MXC_SRPGCR_PCR);
|
~(MXC_SRPGCR_PCR);
|
||||||
empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) &
|
empgc0 = imx_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) &
|
||||||
~(MXC_SRPGCR_PCR);
|
~(MXC_SRPGCR_PCR);
|
||||||
empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) &
|
empgc1 = imx_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) &
|
||||||
~(MXC_SRPGCR_PCR);
|
~(MXC_SRPGCR_PCR);
|
||||||
|
|
||||||
switch (mode) {
|
switch (mode) {
|
||||||
@ -196,17 +196,17 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
__raw_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC);
|
imx_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC);
|
||||||
__raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR);
|
imx_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR);
|
||||||
__raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR);
|
imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR);
|
||||||
__raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR);
|
imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR);
|
||||||
|
|
||||||
if (stop_mode) {
|
if (stop_mode) {
|
||||||
empgc0 |= MXC_SRPGCR_PCR;
|
empgc0 |= MXC_SRPGCR_PCR;
|
||||||
empgc1 |= MXC_SRPGCR_PCR;
|
empgc1 |= MXC_SRPGCR_PCR;
|
||||||
|
|
||||||
__raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
|
imx_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
|
||||||
__raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
|
imx_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -228,8 +228,8 @@ static int mx5_suspend_enter(suspend_state_t state)
|
|||||||
flush_cache_all();
|
flush_cache_all();
|
||||||
|
|
||||||
/*clear the EMPGC0/1 bits */
|
/*clear the EMPGC0/1 bits */
|
||||||
__raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
|
imx_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
|
||||||
__raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
|
imx_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
|
||||||
|
|
||||||
if (imx5_suspend_in_ocram_fn)
|
if (imx5_suspend_in_ocram_fn)
|
||||||
imx5_suspend_in_ocram_fn(suspend_ocram_base);
|
imx5_suspend_in_ocram_fn(suspend_ocram_base);
|
||||||
|
@ -561,13 +561,13 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
|
|||||||
goto put_node;
|
goto put_node;
|
||||||
|
|
||||||
pl310_cache_map_failed:
|
pl310_cache_map_failed:
|
||||||
iounmap(&pm_info->gpc_base.vbase);
|
iounmap(pm_info->gpc_base.vbase);
|
||||||
gpc_map_failed:
|
gpc_map_failed:
|
||||||
iounmap(&pm_info->iomuxc_base.vbase);
|
iounmap(pm_info->iomuxc_base.vbase);
|
||||||
iomuxc_map_failed:
|
iomuxc_map_failed:
|
||||||
iounmap(&pm_info->src_base.vbase);
|
iounmap(pm_info->src_base.vbase);
|
||||||
src_map_failed:
|
src_map_failed:
|
||||||
iounmap(&pm_info->mmdc_base.vbase);
|
iounmap(pm_info->mmdc_base.vbase);
|
||||||
put_node:
|
put_node:
|
||||||
of_node_put(node);
|
of_node_put(node);
|
||||||
|
|
||||||
|
@ -73,7 +73,7 @@ static int imx_src_reset_module(struct reset_controller_dev *rcdev,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct reset_control_ops imx_src_ops = {
|
static const struct reset_control_ops imx_src_ops = {
|
||||||
.reset = imx_src_reset_module,
|
.reset = imx_src_reset_module,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -54,7 +54,7 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
|
|||||||
wcr_enable = (1 << 2);
|
wcr_enable = (1 << 2);
|
||||||
|
|
||||||
/* Assert SRS signal */
|
/* Assert SRS signal */
|
||||||
__raw_writew(wcr_enable, wdog_base);
|
imx_writew(wcr_enable, wdog_base);
|
||||||
/*
|
/*
|
||||||
* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
|
* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
|
||||||
* written twice), we add another two writes to ensure there must be at
|
* written twice), we add another two writes to ensure there must be at
|
||||||
@ -62,8 +62,8 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
|
|||||||
* the target check here, since the writes shouldn't be a huge burden
|
* the target check here, since the writes shouldn't be a huge burden
|
||||||
* for other platforms.
|
* for other platforms.
|
||||||
*/
|
*/
|
||||||
__raw_writew(wcr_enable, wdog_base);
|
imx_writew(wcr_enable, wdog_base);
|
||||||
__raw_writew(wcr_enable, wdog_base);
|
imx_writew(wcr_enable, wdog_base);
|
||||||
|
|
||||||
/* wait for reset to assert... */
|
/* wait for reset to assert... */
|
||||||
mdelay(500);
|
mdelay(500);
|
||||||
@ -106,6 +106,9 @@ void __init imx_init_l2cache(void)
|
|||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)
|
||||||
|
goto skip_if_enabled;
|
||||||
|
|
||||||
/* Configure the L2 PREFETCH and POWER registers */
|
/* Configure the L2 PREFETCH and POWER registers */
|
||||||
val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
|
val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
|
||||||
val |= 0x70800000;
|
val |= 0x70800000;
|
||||||
@ -122,6 +125,7 @@ void __init imx_init_l2cache(void)
|
|||||||
val &= ~(1 << 30 | 1 << 23);
|
val &= ~(1 << 30 | 1 << 23);
|
||||||
writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
|
writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
|
||||||
|
|
||||||
|
skip_if_enabled:
|
||||||
iounmap(l2x0_base);
|
iounmap(l2x0_base);
|
||||||
of_node_put(np);
|
of_node_put(np);
|
||||||
|
|
||||||
|
@ -65,10 +65,10 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
|
|||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
mask = 1U << (irq & 0x1F);
|
mask = 1U << (irq & 0x1F);
|
||||||
|
|
||||||
value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
|
value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
|
||||||
if (type)
|
if (type)
|
||||||
value &= ~mask;
|
value &= ~mask;
|
||||||
__raw_writel(value, tzic_base + TZIC_INTSEC0(index));
|
imx_writel(value, tzic_base + TZIC_INTSEC0(index));
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
@ -82,15 +82,15 @@ static void tzic_irq_suspend(struct irq_data *d)
|
|||||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||||
int idx = d->hwirq >> 5;
|
int idx = d->hwirq >> 5;
|
||||||
|
|
||||||
__raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
|
imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tzic_irq_resume(struct irq_data *d)
|
static void tzic_irq_resume(struct irq_data *d)
|
||||||
{
|
{
|
||||||
int idx = d->hwirq >> 5;
|
int idx = d->hwirq >> 5;
|
||||||
|
|
||||||
__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
|
imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)),
|
||||||
tzic_base + TZIC_WAKEUP0(idx));
|
tzic_base + TZIC_WAKEUP0(idx));
|
||||||
}
|
}
|
||||||
|
|
||||||
#else
|
#else
|
||||||
@ -135,8 +135,8 @@ static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
|
|||||||
handled = 0;
|
handled = 0;
|
||||||
|
|
||||||
for (i = 0; i < 4; i++) {
|
for (i = 0; i < 4; i++) {
|
||||||
stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
|
stat = imx_readl(tzic_base + TZIC_HIPND(i)) &
|
||||||
__raw_readl(tzic_base + TZIC_INTSEC0(i));
|
imx_readl(tzic_base + TZIC_INTSEC0(i));
|
||||||
|
|
||||||
while (stat) {
|
while (stat) {
|
||||||
handled = 1;
|
handled = 1;
|
||||||
@ -166,18 +166,18 @@ void __init tzic_init_irq(void)
|
|||||||
/* put the TZIC into the reset value with
|
/* put the TZIC into the reset value with
|
||||||
* all interrupts disabled
|
* all interrupts disabled
|
||||||
*/
|
*/
|
||||||
i = __raw_readl(tzic_base + TZIC_INTCNTL);
|
i = imx_readl(tzic_base + TZIC_INTCNTL);
|
||||||
|
|
||||||
__raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
|
imx_writel(0x80010001, tzic_base + TZIC_INTCNTL);
|
||||||
__raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
|
imx_writel(0x1f, tzic_base + TZIC_PRIOMASK);
|
||||||
__raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
|
imx_writel(0x02, tzic_base + TZIC_SYNCCTRL);
|
||||||
|
|
||||||
for (i = 0; i < 4; i++)
|
for (i = 0; i < 4; i++)
|
||||||
__raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
|
imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
|
||||||
|
|
||||||
/* disable all interrupts */
|
/* disable all interrupts */
|
||||||
for (i = 0; i < 4; i++)
|
for (i = 0; i < 4; i++)
|
||||||
__raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
|
imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
|
||||||
|
|
||||||
/* all IRQ no FIQ Warning :: No selection */
|
/* all IRQ no FIQ Warning :: No selection */
|
||||||
|
|
||||||
@ -214,13 +214,13 @@ int tzic_enable_wake(void)
|
|||||||
{
|
{
|
||||||
unsigned int i;
|
unsigned int i;
|
||||||
|
|
||||||
__raw_writel(1, tzic_base + TZIC_DSMINT);
|
imx_writel(1, tzic_base + TZIC_DSMINT);
|
||||||
if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
|
if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0))
|
||||||
return -EAGAIN;
|
return -EAGAIN;
|
||||||
|
|
||||||
for (i = 0; i < 4; i++)
|
for (i = 0; i < 4; i++)
|
||||||
__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)),
|
imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)),
|
||||||
tzic_base + TZIC_WAKEUP0(i));
|
tzic_base + TZIC_WAKEUP0(i));
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -44,13 +44,21 @@ static const struct mtk_smp_boot_info mtk_mt6589_boot = {
|
|||||||
{ 0x38, 0x3c, 0x40 },
|
{ 0x38, 0x3c, 0x40 },
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct mtk_smp_boot_info mtk_mt7623_boot = {
|
||||||
|
0x10202000, 0x34,
|
||||||
|
{ 0x534c4131, 0x4c415332, 0x41534c33 },
|
||||||
|
{ 0x38, 0x3c, 0x40 },
|
||||||
|
};
|
||||||
|
|
||||||
static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
|
static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
|
||||||
{ .compatible = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
|
{ .compatible = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
|
||||||
{ .compatible = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
|
{ .compatible = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
|
||||||
|
{ .compatible = "mediatek,mt2701", .data = &mtk_mt8135_tz_boot },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
|
static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
|
||||||
{ .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot },
|
{ .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot },
|
||||||
|
{ .compatible = "mediatek,mt7623", .data = &mtk_mt7623_boot },
|
||||||
};
|
};
|
||||||
|
|
||||||
static void __iomem *mtk_smp_base;
|
static void __iomem *mtk_smp_base;
|
||||||
|
@ -25,6 +25,7 @@
|
|||||||
#include <linux/device.h>
|
#include <linux/device.h>
|
||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
#include <linux/dma-mapping.h>
|
#include <linux/dma-mapping.h>
|
||||||
|
#include <linux/dmaengine.h>
|
||||||
#include <linux/omap-dma.h>
|
#include <linux/omap-dma.h>
|
||||||
#include <mach/tc.h>
|
#include <mach/tc.h>
|
||||||
|
|
||||||
@ -265,6 +266,42 @@ static const struct platform_device_info omap_dma_dev_info = {
|
|||||||
.num_res = 1,
|
.num_res = 1,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* OMAP730, OMAP850 */
|
||||||
|
static const struct dma_slave_map omap7xx_sdma_map[] = {
|
||||||
|
{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
|
||||||
|
{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
|
||||||
|
{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(10) },
|
||||||
|
{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(11) },
|
||||||
|
{ "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
|
||||||
|
{ "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
|
||||||
|
{ "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
|
||||||
|
{ "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
|
||||||
|
{ "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
|
||||||
|
{ "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
|
||||||
|
{ "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
|
||||||
|
{ "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
|
||||||
|
};
|
||||||
|
|
||||||
|
/* OMAP1510, OMAP1610*/
|
||||||
|
static const struct dma_slave_map omap1xxx_sdma_map[] = {
|
||||||
|
{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
|
||||||
|
{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
|
||||||
|
{ "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(10) },
|
||||||
|
{ "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(11) },
|
||||||
|
{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(16) },
|
||||||
|
{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(17) },
|
||||||
|
{ "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
|
||||||
|
{ "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
|
||||||
|
{ "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
|
||||||
|
{ "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
|
||||||
|
{ "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
|
||||||
|
{ "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
|
||||||
|
{ "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
|
||||||
|
{ "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
|
||||||
|
{ "mmci-omap.1", "tx", SDMA_FILTER_PARAM(54) },
|
||||||
|
{ "mmci-omap.1", "rx", SDMA_FILTER_PARAM(55) },
|
||||||
|
};
|
||||||
|
|
||||||
static struct omap_system_dma_plat_info dma_plat_info __initdata = {
|
static struct omap_system_dma_plat_info dma_plat_info __initdata = {
|
||||||
.reg_map = reg_map,
|
.reg_map = reg_map,
|
||||||
.channel_stride = 0x40,
|
.channel_stride = 0x40,
|
||||||
@ -342,6 +379,14 @@ static int __init omap1_system_dma_init(void)
|
|||||||
p.dma_attr = d;
|
p.dma_attr = d;
|
||||||
p.errata = configure_dma_errata();
|
p.errata = configure_dma_errata();
|
||||||
|
|
||||||
|
if (cpu_is_omap7xx()) {
|
||||||
|
p.slave_map = omap7xx_sdma_map;
|
||||||
|
p.slavecnt = ARRAY_SIZE(omap7xx_sdma_map);
|
||||||
|
} else {
|
||||||
|
p.slave_map = omap1xxx_sdma_map;
|
||||||
|
p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map);
|
||||||
|
}
|
||||||
|
|
||||||
ret = platform_device_add_data(pdev, &p, sizeof(p));
|
ret = platform_device_add_data(pdev, &p, sizeof(p));
|
||||||
if (ret) {
|
if (ret) {
|
||||||
dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
|
dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
|
||||||
|
@ -28,6 +28,7 @@
|
|||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
#include <linux/device.h>
|
#include <linux/device.h>
|
||||||
#include <linux/dma-mapping.h>
|
#include <linux/dma-mapping.h>
|
||||||
|
#include <linux/dmaengine.h>
|
||||||
#include <linux/of.h>
|
#include <linux/of.h>
|
||||||
#include <linux/omap-dma.h>
|
#include <linux/omap-dma.h>
|
||||||
|
|
||||||
@ -203,6 +204,108 @@ static unsigned configure_dma_errata(void)
|
|||||||
return errata;
|
return errata;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static const struct dma_slave_map omap24xx_sdma_map[] = {
|
||||||
|
{ "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
|
||||||
|
{ "omap-aes", "tx", SDMA_FILTER_PARAM(9) },
|
||||||
|
{ "omap-aes", "rx", SDMA_FILTER_PARAM(10) },
|
||||||
|
{ "omap-sham", "rx", SDMA_FILTER_PARAM(13) },
|
||||||
|
{ "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
|
||||||
|
{ "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
|
||||||
|
{ "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
|
||||||
|
{ "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
|
||||||
|
{ "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
|
||||||
|
{ "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
|
||||||
|
{ "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
|
||||||
|
{ "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
|
||||||
|
{ "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
|
||||||
|
{ "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
|
||||||
|
{ "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
|
||||||
|
{ "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
|
||||||
|
{ "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
|
||||||
|
{ "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
|
||||||
|
{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
|
||||||
|
{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
|
||||||
|
{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
|
||||||
|
{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
|
||||||
|
{ "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
|
||||||
|
{ "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
|
||||||
|
{ "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
|
||||||
|
{ "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
|
||||||
|
{ "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
|
||||||
|
{ "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
|
||||||
|
{ "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
|
||||||
|
{ "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
|
||||||
|
{ "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
|
||||||
|
{ "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
|
||||||
|
{ "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
|
||||||
|
{ "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
|
||||||
|
{ "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
|
||||||
|
{ "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
|
||||||
|
{ "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
|
||||||
|
{ "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
|
||||||
|
{ "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
|
||||||
|
{ "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
|
||||||
|
{ "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
|
||||||
|
{ "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
|
||||||
|
{ "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
|
||||||
|
{ "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct dma_slave_map omap3xxx_sdma_map[] = {
|
||||||
|
{ "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
|
||||||
|
{ "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
|
||||||
|
{ "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
|
||||||
|
{ "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
|
||||||
|
{ "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
|
||||||
|
{ "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
|
||||||
|
{ "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
|
||||||
|
{ "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
|
||||||
|
{ "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
|
||||||
|
{ "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
|
||||||
|
{ "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
|
||||||
|
{ "omap_i2c.3", "tx", SDMA_FILTER_PARAM(25) },
|
||||||
|
{ "omap_i2c.3", "rx", SDMA_FILTER_PARAM(26) },
|
||||||
|
{ "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
|
||||||
|
{ "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
|
||||||
|
{ "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
|
||||||
|
{ "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
|
||||||
|
{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
|
||||||
|
{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
|
||||||
|
{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
|
||||||
|
{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
|
||||||
|
{ "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
|
||||||
|
{ "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
|
||||||
|
{ "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
|
||||||
|
{ "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
|
||||||
|
{ "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
|
||||||
|
{ "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
|
||||||
|
{ "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
|
||||||
|
{ "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
|
||||||
|
{ "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
|
||||||
|
{ "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
|
||||||
|
{ "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
|
||||||
|
{ "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
|
||||||
|
{ "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
|
||||||
|
{ "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
|
||||||
|
{ "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
|
||||||
|
{ "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
|
||||||
|
{ "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
|
||||||
|
{ "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
|
||||||
|
{ "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
|
||||||
|
{ "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
|
||||||
|
{ "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
|
||||||
|
{ "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
|
||||||
|
{ "omap-aes", "tx", SDMA_FILTER_PARAM(65) },
|
||||||
|
{ "omap-aes", "rx", SDMA_FILTER_PARAM(66) },
|
||||||
|
{ "omap-sham", "rx", SDMA_FILTER_PARAM(69) },
|
||||||
|
{ "omap2_mcspi.3", "tx0", SDMA_FILTER_PARAM(70) },
|
||||||
|
{ "omap2_mcspi.3", "rx0", SDMA_FILTER_PARAM(71) },
|
||||||
|
{ "omap_hsmmc.2", "tx", SDMA_FILTER_PARAM(77) },
|
||||||
|
{ "omap_hsmmc.2", "rx", SDMA_FILTER_PARAM(78) },
|
||||||
|
{ "omap_uart.3", "tx", SDMA_FILTER_PARAM(81) },
|
||||||
|
{ "omap_uart.3", "rx", SDMA_FILTER_PARAM(82) },
|
||||||
|
};
|
||||||
|
|
||||||
static struct omap_system_dma_plat_info dma_plat_info __initdata = {
|
static struct omap_system_dma_plat_info dma_plat_info __initdata = {
|
||||||
.reg_map = reg_map,
|
.reg_map = reg_map,
|
||||||
.channel_stride = 0x60,
|
.channel_stride = 0x60,
|
||||||
@ -231,6 +334,20 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
|
|||||||
p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
|
p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
|
||||||
p.errata = configure_dma_errata();
|
p.errata = configure_dma_errata();
|
||||||
|
|
||||||
|
if (!of_have_populated_dt()) {
|
||||||
|
if (soc_is_omap24xx()) {
|
||||||
|
p.slave_map = omap24xx_sdma_map;
|
||||||
|
p.slavecnt = ARRAY_SIZE(omap24xx_sdma_map);
|
||||||
|
} else if (soc_is_omap34xx() || soc_is_omap3630()) {
|
||||||
|
p.slave_map = omap3xxx_sdma_map;
|
||||||
|
p.slavecnt = ARRAY_SIZE(omap3xxx_sdma_map);
|
||||||
|
} else {
|
||||||
|
pr_err("%s: The legacy DMA map is not provided!\n",
|
||||||
|
__func__);
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
|
pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
|
||||||
if (IS_ERR(pdev)) {
|
if (IS_ERR(pdev)) {
|
||||||
pr_err("%s: Can't build omap_device for %s:%s.\n",
|
pr_err("%s: Can't build omap_device for %s:%s.\n",
|
||||||
|
@ -1020,9 +1020,21 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
|
|||||||
NULL,
|
NULL,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
|
||||||
|
&am33xx_l4_wkup__rtc,
|
||||||
|
NULL,
|
||||||
|
};
|
||||||
|
|
||||||
int __init am43xx_hwmod_init(void)
|
int __init am43xx_hwmod_init(void)
|
||||||
{
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
omap_hwmod_am43xx_reg();
|
omap_hwmod_am43xx_reg();
|
||||||
omap_hwmod_init();
|
omap_hwmod_init();
|
||||||
return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
|
ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
|
||||||
|
|
||||||
|
if (!ret && of_machine_is_compatible("ti,am4372"))
|
||||||
|
ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
|
||||||
|
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
@ -429,6 +429,67 @@ static struct omap_hwmod dra7xx_dma_system_hwmod = {
|
|||||||
.dev_attr = &dma_dev_attr,
|
.dev_attr = &dma_dev_attr,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 'tpcc' class
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
|
||||||
|
.name = "tpcc",
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct omap_hwmod dra7xx_tpcc_hwmod = {
|
||||||
|
.name = "tpcc",
|
||||||
|
.class = &dra7xx_tpcc_hwmod_class,
|
||||||
|
.clkdm_name = "l3main1_clkdm",
|
||||||
|
.main_clk = "l3_iclk_div",
|
||||||
|
.prcm = {
|
||||||
|
.omap4 = {
|
||||||
|
.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
|
||||||
|
.context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 'tptc' class
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
|
||||||
|
.name = "tptc",
|
||||||
|
};
|
||||||
|
|
||||||
|
/* tptc0 */
|
||||||
|
static struct omap_hwmod dra7xx_tptc0_hwmod = {
|
||||||
|
.name = "tptc0",
|
||||||
|
.class = &dra7xx_tptc_hwmod_class,
|
||||||
|
.clkdm_name = "l3main1_clkdm",
|
||||||
|
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
||||||
|
.main_clk = "l3_iclk_div",
|
||||||
|
.prcm = {
|
||||||
|
.omap4 = {
|
||||||
|
.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
|
||||||
|
.context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
|
||||||
|
.modulemode = MODULEMODE_HWCTRL,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
/* tptc1 */
|
||||||
|
static struct omap_hwmod dra7xx_tptc1_hwmod = {
|
||||||
|
.name = "tptc1",
|
||||||
|
.class = &dra7xx_tptc_hwmod_class,
|
||||||
|
.clkdm_name = "l3main1_clkdm",
|
||||||
|
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
||||||
|
.main_clk = "l3_iclk_div",
|
||||||
|
.prcm = {
|
||||||
|
.omap4 = {
|
||||||
|
.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
|
||||||
|
.context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
|
||||||
|
.modulemode = MODULEMODE_HWCTRL,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* 'dss' class
|
* 'dss' class
|
||||||
*
|
*
|
||||||
@ -1526,8 +1587,31 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
|
|||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* As noted in documentation for _reset() in omap_hwmod.c, the stock reset
|
||||||
|
* functionality of OMAP HWMOD layer does not deassert the hardreset lines
|
||||||
|
* associated with an IP automatically leaving the driver to handle that
|
||||||
|
* by itself. This does not work for PCIeSS which needs the reset lines
|
||||||
|
* deasserted for the driver to start accessing registers.
|
||||||
|
*
|
||||||
|
* We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
|
||||||
|
* lines after asserting them.
|
||||||
|
*/
|
||||||
|
static int dra7xx_pciess_reset(struct omap_hwmod *oh)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < oh->rst_lines_cnt; i++) {
|
||||||
|
omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
|
||||||
|
omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
|
static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
|
||||||
.name = "pcie",
|
.name = "pcie",
|
||||||
|
.reset = dra7xx_pciess_reset,
|
||||||
};
|
};
|
||||||
|
|
||||||
/* pcie1 */
|
/* pcie1 */
|
||||||
@ -2563,6 +2647,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
|
|||||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* l3_main_1 -> tpcc */
|
||||||
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
|
||||||
|
.master = &dra7xx_l3_main_1_hwmod,
|
||||||
|
.slave = &dra7xx_tpcc_hwmod,
|
||||||
|
.clk = "l3_iclk_div",
|
||||||
|
.user = OCP_USER_MPU,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* l3_main_1 -> tptc0 */
|
||||||
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
|
||||||
|
.master = &dra7xx_l3_main_1_hwmod,
|
||||||
|
.slave = &dra7xx_tptc0_hwmod,
|
||||||
|
.clk = "l3_iclk_div",
|
||||||
|
.user = OCP_USER_MPU,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* l3_main_1 -> tptc1 */
|
||||||
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
|
||||||
|
.master = &dra7xx_l3_main_1_hwmod,
|
||||||
|
.slave = &dra7xx_tptc1_hwmod,
|
||||||
|
.clk = "l3_iclk_div",
|
||||||
|
.user = OCP_USER_MPU,
|
||||||
|
};
|
||||||
|
|
||||||
static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
|
static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
|
||||||
{
|
{
|
||||||
.name = "family",
|
.name = "family",
|
||||||
@ -3380,6 +3488,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
|||||||
&dra7xx_l3_main_1__mcasp3,
|
&dra7xx_l3_main_1__mcasp3,
|
||||||
&dra7xx_gmac__mdio,
|
&dra7xx_gmac__mdio,
|
||||||
&dra7xx_l4_cfg__dma_system,
|
&dra7xx_l4_cfg__dma_system,
|
||||||
|
&dra7xx_l3_main_1__tpcc,
|
||||||
|
&dra7xx_l3_main_1__tptc0,
|
||||||
|
&dra7xx_l3_main_1__tptc1,
|
||||||
&dra7xx_l3_main_1__dss,
|
&dra7xx_l3_main_1__dss,
|
||||||
&dra7xx_l3_main_1__dispc,
|
&dra7xx_l3_main_1__dispc,
|
||||||
&dra7xx_l3_main_1__hdmi,
|
&dra7xx_l3_main_1__hdmi,
|
||||||
|
@ -228,6 +228,42 @@ static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
|
|||||||
.user = OCP_USER_MPU,
|
.user = OCP_USER_MPU,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* RTC */
|
||||||
|
static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = {
|
||||||
|
.rev_offs = 0x74,
|
||||||
|
.sysc_offs = 0x78,
|
||||||
|
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
||||||
|
.idlemodes = SIDLE_FORCE | SIDLE_NO |
|
||||||
|
SIDLE_SMART | SIDLE_SMART_WKUP,
|
||||||
|
.sysc_fields = &omap_hwmod_sysc_type3,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
|
||||||
|
.name = "rtc",
|
||||||
|
.sysc = &ti81xx_rtc_sysc,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct omap_hwmod ti81xx_rtc_hwmod = {
|
||||||
|
.name = "rtc",
|
||||||
|
.class = &ti81xx_rtc_hwmod_class,
|
||||||
|
.clkdm_name = "alwon_l3s_clkdm",
|
||||||
|
.flags = HWMOD_NO_IDLEST,
|
||||||
|
.main_clk = "sysclk18_ck",
|
||||||
|
.prcm = {
|
||||||
|
.omap4 = {
|
||||||
|
.clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
|
||||||
|
.modulemode = MODULEMODE_SWCTRL,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = {
|
||||||
|
.master = &dm81xx_l4_ls_hwmod,
|
||||||
|
.slave = &ti81xx_rtc_hwmod,
|
||||||
|
.clk = "sysclk6_ck",
|
||||||
|
.user = OCP_USER_MPU,
|
||||||
|
};
|
||||||
|
|
||||||
/* UART common */
|
/* UART common */
|
||||||
static struct omap_hwmod_class_sysconfig uart_sysc = {
|
static struct omap_hwmod_class_sysconfig uart_sysc = {
|
||||||
.rev_offs = 0x50,
|
.rev_offs = 0x50,
|
||||||
@ -1381,6 +1417,7 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
|
|||||||
&dm81xx_l4_ls__mcspi1,
|
&dm81xx_l4_ls__mcspi1,
|
||||||
&dm814x_l4_ls__mmc1,
|
&dm814x_l4_ls__mmc1,
|
||||||
&dm814x_l4_ls__mmc2,
|
&dm814x_l4_ls__mmc2,
|
||||||
|
&ti81xx_l4_ls__rtc,
|
||||||
&dm81xx_alwon_l3_fast__tpcc,
|
&dm81xx_alwon_l3_fast__tpcc,
|
||||||
&dm81xx_alwon_l3_fast__tptc0,
|
&dm81xx_alwon_l3_fast__tptc0,
|
||||||
&dm81xx_alwon_l3_fast__tptc1,
|
&dm81xx_alwon_l3_fast__tptc1,
|
||||||
@ -1420,6 +1457,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
|
|||||||
&dm81xx_l4_ls__gpio1,
|
&dm81xx_l4_ls__gpio1,
|
||||||
&dm81xx_l4_ls__gpio2,
|
&dm81xx_l4_ls__gpio2,
|
||||||
&dm81xx_l4_ls__elm,
|
&dm81xx_l4_ls__elm,
|
||||||
|
&ti81xx_l4_ls__rtc,
|
||||||
&dm816x_l4_ls__mmc1,
|
&dm816x_l4_ls__mmc1,
|
||||||
&dm816x_l4_ls__timer1,
|
&dm816x_l4_ls__timer1,
|
||||||
&dm816x_l4_ls__timer2,
|
&dm816x_l4_ls__timer2,
|
||||||
|
@ -181,6 +181,14 @@ static inline int is_ti ##class (void) \
|
|||||||
return (GET_TI_CLASS == (id)) ? 1 : 0; \
|
return (GET_TI_CLASS == (id)) ? 1 : 0; \
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#define GET_DRA_CLASS ((omap_rev() >> 24) & 0xff)
|
||||||
|
|
||||||
|
#define IS_DRA_CLASS(class, id) \
|
||||||
|
static inline int is_dra ##class (void) \
|
||||||
|
{ \
|
||||||
|
return (GET_DRA_CLASS == (id)) ? 1 : 0; \
|
||||||
|
}
|
||||||
|
|
||||||
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
|
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
|
||||||
|
|
||||||
#define IS_OMAP_SUBCLASS(subclass, id) \
|
#define IS_OMAP_SUBCLASS(subclass, id) \
|
||||||
@ -201,6 +209,12 @@ static inline int is_am ##subclass (void) \
|
|||||||
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
|
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#define IS_DRA_SUBCLASS(subclass, id) \
|
||||||
|
static inline int is_dra ##subclass (void) \
|
||||||
|
{ \
|
||||||
|
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
|
||||||
|
}
|
||||||
|
|
||||||
IS_OMAP_CLASS(24xx, 0x24)
|
IS_OMAP_CLASS(24xx, 0x24)
|
||||||
IS_OMAP_CLASS(34xx, 0x34)
|
IS_OMAP_CLASS(34xx, 0x34)
|
||||||
IS_OMAP_CLASS(44xx, 0x44)
|
IS_OMAP_CLASS(44xx, 0x44)
|
||||||
@ -210,6 +224,7 @@ IS_AM_CLASS(33xx, 0x33)
|
|||||||
IS_AM_CLASS(43xx, 0x43)
|
IS_AM_CLASS(43xx, 0x43)
|
||||||
|
|
||||||
IS_TI_CLASS(81xx, 0x81)
|
IS_TI_CLASS(81xx, 0x81)
|
||||||
|
IS_DRA_CLASS(7xx, 0x7)
|
||||||
|
|
||||||
IS_OMAP_SUBCLASS(242x, 0x242)
|
IS_OMAP_SUBCLASS(242x, 0x242)
|
||||||
IS_OMAP_SUBCLASS(243x, 0x243)
|
IS_OMAP_SUBCLASS(243x, 0x243)
|
||||||
@ -224,6 +239,8 @@ IS_TI_SUBCLASS(816x, 0x816)
|
|||||||
IS_TI_SUBCLASS(814x, 0x814)
|
IS_TI_SUBCLASS(814x, 0x814)
|
||||||
IS_AM_SUBCLASS(335x, 0x335)
|
IS_AM_SUBCLASS(335x, 0x335)
|
||||||
IS_AM_SUBCLASS(437x, 0x437)
|
IS_AM_SUBCLASS(437x, 0x437)
|
||||||
|
IS_DRA_SUBCLASS(75x, 0x75)
|
||||||
|
IS_DRA_SUBCLASS(72x, 0x72)
|
||||||
|
|
||||||
#define soc_is_omap24xx() 0
|
#define soc_is_omap24xx() 0
|
||||||
#define soc_is_omap242x() 0
|
#define soc_is_omap242x() 0
|
||||||
@ -397,9 +414,9 @@ IS_OMAP_TYPE(3430, 0x3430)
|
|||||||
#undef soc_is_dra7xx
|
#undef soc_is_dra7xx
|
||||||
#undef soc_is_dra74x
|
#undef soc_is_dra74x
|
||||||
#undef soc_is_dra72x
|
#undef soc_is_dra72x
|
||||||
#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
|
#define soc_is_dra7xx() is_dra7xx()
|
||||||
#define soc_is_dra74x() (of_machine_is_compatible("ti,dra74"))
|
#define soc_is_dra74x() is_dra75x()
|
||||||
#define soc_is_dra72x() (of_machine_is_compatible("ti,dra72"))
|
#define soc_is_dra72x() is_dra72x()
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Various silicon revisions for omap2 */
|
/* Various silicon revisions for omap2 */
|
||||||
|
@ -297,7 +297,6 @@ config MACH_MAGICIAN
|
|||||||
|
|
||||||
config MACH_MIOA701
|
config MACH_MIOA701
|
||||||
bool "Mitac Mio A701 Support"
|
bool "Mitac Mio A701 Support"
|
||||||
select GPIO_SYSFS
|
|
||||||
select IWMMXT
|
select IWMMXT
|
||||||
select PXA27x
|
select PXA27x
|
||||||
help
|
help
|
||||||
@ -529,7 +528,7 @@ config MACH_TOSA
|
|||||||
|
|
||||||
config TOSA_BT
|
config TOSA_BT
|
||||||
tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
|
tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
|
||||||
depends on MACH_TOSA
|
depends on MACH_TOSA && NET
|
||||||
select RFKILL
|
select RFKILL
|
||||||
help
|
help
|
||||||
This is a simple driver that is able to control
|
This is a simple driver that is able to control
|
||||||
|
@ -1203,6 +1203,7 @@ void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
|
|||||||
|
|
||||||
static struct mmp_dma_platdata pxa_dma_pdata = {
|
static struct mmp_dma_platdata pxa_dma_pdata = {
|
||||||
.dma_channels = 0,
|
.dma_channels = 0,
|
||||||
|
.nb_requestors = 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource pxa_dma_resource[] = {
|
static struct resource pxa_dma_resource[] = {
|
||||||
@ -1231,7 +1232,7 @@ static struct platform_device pxa2xx_pxa_dma = {
|
|||||||
.resource = pxa_dma_resource,
|
.resource = pxa_dma_resource,
|
||||||
};
|
};
|
||||||
|
|
||||||
void __init pxa2xx_set_dmac_info(int nb_channels)
|
void __init pxa2xx_set_dmac_info(int nb_channels, int nb_requestors)
|
||||||
{
|
{
|
||||||
pxa_dma_pdata.dma_channels = nb_channels;
|
pxa_dma_pdata.dma_channels = nb_channels;
|
||||||
pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
|
pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
|
||||||
|
@ -57,7 +57,7 @@ struct gpio_vbus_mach_info e7xx_udc_info = {
|
|||||||
.gpio_pullup_inverted = 1
|
.gpio_pullup_inverted = 1
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device e7xx_gpio_vbus = {
|
static struct platform_device e7xx_gpio_vbus __maybe_unused = {
|
||||||
.name = "gpio-vbus",
|
.name = "gpio-vbus",
|
||||||
.id = -1,
|
.id = -1,
|
||||||
.dev = {
|
.dev = {
|
||||||
@ -126,7 +126,7 @@ struct resource eseries_tmio_resources[] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
/* Some e-series hardware cannot control the 32K clock */
|
/* Some e-series hardware cannot control the 32K clock */
|
||||||
static void __init eseries_register_clks(void)
|
static void __init __maybe_unused eseries_register_clks(void)
|
||||||
{
|
{
|
||||||
clk_register_fixed_rate(NULL, "CLK_CK32K", NULL, CLK_IS_ROOT, 32768);
|
clk_register_fixed_rate(NULL, "CLK_CK32K", NULL, CLK_IS_ROOT, 32768);
|
||||||
}
|
}
|
||||||
|
@ -139,14 +139,14 @@ static void gumstix_setup_bt_clock(void)
|
|||||||
{
|
{
|
||||||
int timeout = 500;
|
int timeout = 500;
|
||||||
|
|
||||||
if (!(OSCC & OSCC_OOK))
|
if (!(readl(OSCC) & OSCC_OOK))
|
||||||
pr_warn("32kHz clock was not on. Bootloader may need to be updated\n");
|
pr_warn("32kHz clock was not on. Bootloader may need to be updated\n");
|
||||||
else
|
else
|
||||||
return;
|
return;
|
||||||
|
|
||||||
OSCC |= OSCC_OON;
|
writel(readl(OSCC) | OSCC_OON, OSCC);
|
||||||
do {
|
do {
|
||||||
if (OSCC & OSCC_OOK)
|
if (readl(OSCC) & OSCC_OOK)
|
||||||
break;
|
break;
|
||||||
udelay(1);
|
udelay(1);
|
||||||
} while (--timeout);
|
} while (--timeout);
|
||||||
|
@ -134,10 +134,10 @@
|
|||||||
/*
|
/*
|
||||||
* PXA2xx specific Core clock definitions
|
* PXA2xx specific Core clock definitions
|
||||||
*/
|
*/
|
||||||
#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
|
#define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */
|
||||||
#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
|
#define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */
|
||||||
#define CKEN __REG(0x41300004) /* Clock Enable Register */
|
#define CKEN io_p2v(0x41300004) /* Clock Enable Register */
|
||||||
#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
|
#define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */
|
||||||
|
|
||||||
#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
|
#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
|
||||||
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
|
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
|
||||||
|
@ -18,7 +18,7 @@
|
|||||||
/*
|
/*
|
||||||
* Oscillator Configuration Register (OSCC)
|
* Oscillator Configuration Register (OSCC)
|
||||||
*/
|
*/
|
||||||
#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */
|
#define OSCC io_p2v(0x41350000) /* Oscillator Configuration Register */
|
||||||
|
|
||||||
#define OSCC_PEN (1 << 11) /* 13MHz POUT */
|
#define OSCC_PEN (1 << 11) /* 13MHz POUT */
|
||||||
|
|
||||||
|
@ -29,6 +29,9 @@ extern int pxa_pm_enter(suspend_state_t state);
|
|||||||
extern int pxa_pm_prepare(void);
|
extern int pxa_pm_prepare(void);
|
||||||
extern void pxa_pm_finish(void);
|
extern void pxa_pm_finish(void);
|
||||||
|
|
||||||
|
extern const char pm_enter_standby_start[], pm_enter_standby_end[];
|
||||||
|
extern int pxa3xx_finish_suspend(unsigned long);
|
||||||
|
|
||||||
/* NOTE: this is for PM debugging on Lubbock, it's really a big
|
/* NOTE: this is for PM debugging on Lubbock, it's really a big
|
||||||
* ugly, but let's keep the crap minimum here, instead of direct
|
* ugly, but let's keep the crap minimum here, instead of direct
|
||||||
* accessing the LUBBOCK CPLD registers in arch/arm/mach-pxa/pm.c
|
* accessing the LUBBOCK CPLD registers in arch/arm/mach-pxa/pm.c
|
||||||
|
@ -19,42 +19,18 @@
|
|||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
|
||||||
#ifdef CONFIG_PXA3xx
|
#ifdef CONFIG_PXA3xx
|
||||||
static const struct of_dev_auxdata const pxa3xx_auxdata_lookup[] __initconst = {
|
|
||||||
OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40100000, "pxa2xx-uart.0", NULL),
|
|
||||||
OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40200000, "pxa2xx-uart.1", NULL),
|
|
||||||
OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40700000, "pxa2xx-uart.2", NULL),
|
|
||||||
OF_DEV_AUXDATA("mrvl,pxa-uart", 0x41600000, "pxa2xx-uart.3", NULL),
|
|
||||||
OF_DEV_AUXDATA("marvell,pxa-mmc", 0x41100000, "pxa2xx-mci.0", NULL),
|
|
||||||
OF_DEV_AUXDATA("intel,pxa3xx-gpio", 0x40e00000, "pxa3xx-gpio", NULL),
|
|
||||||
OF_DEV_AUXDATA("marvell,pxa-ohci", 0x4c000000, "pxa27x-ohci", NULL),
|
|
||||||
OF_DEV_AUXDATA("mrvl,pxa-i2c", 0x40301680, "pxa2xx-i2c.0", NULL),
|
|
||||||
OF_DEV_AUXDATA("mrvl,pwri2c", 0x40f500c0, "pxa3xx-i2c.1", NULL),
|
|
||||||
OF_DEV_AUXDATA("marvell,pxa3xx-nand", 0x43100000, "pxa3xx-nand", NULL),
|
|
||||||
{}
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init pxa3xx_dt_init(void)
|
|
||||||
{
|
|
||||||
of_platform_populate(NULL, of_default_bus_match_table,
|
|
||||||
pxa3xx_auxdata_lookup, NULL);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const char *const pxa3xx_dt_board_compat[] __initconst = {
|
static const char *const pxa3xx_dt_board_compat[] __initconst = {
|
||||||
"marvell,pxa300",
|
"marvell,pxa300",
|
||||||
"marvell,pxa310",
|
"marvell,pxa310",
|
||||||
"marvell,pxa320",
|
"marvell,pxa320",
|
||||||
NULL,
|
NULL,
|
||||||
};
|
};
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PXA3xx
|
|
||||||
DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)")
|
DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)")
|
||||||
.map_io = pxa3xx_map_io,
|
.map_io = pxa3xx_map_io,
|
||||||
.init_irq = pxa3xx_dt_init_irq,
|
.init_irq = pxa3xx_dt_init_irq,
|
||||||
.handle_irq = pxa3xx_handle_irq,
|
.handle_irq = pxa3xx_handle_irq,
|
||||||
.init_time = pxa_timer_init,
|
|
||||||
.restart = pxa_restart,
|
.restart = pxa_restart,
|
||||||
.init_machine = pxa3xx_dt_init,
|
|
||||||
.dt_compat = pxa3xx_dt_board_compat,
|
.dt_compat = pxa3xx_dt_board_compat,
|
||||||
MACHINE_END
|
MACHINE_END
|
||||||
#endif
|
#endif
|
||||||
|
@ -206,7 +206,7 @@ static int __init pxa25x_init(void)
|
|||||||
register_syscore_ops(&pxa_irq_syscore_ops);
|
register_syscore_ops(&pxa_irq_syscore_ops);
|
||||||
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
|
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
|
||||||
|
|
||||||
pxa2xx_set_dmac_info(16);
|
pxa2xx_set_dmac_info(16, 40);
|
||||||
pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info);
|
pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info);
|
||||||
ret = platform_add_devices(pxa25x_devices,
|
ret = platform_add_devices(pxa25x_devices,
|
||||||
ARRAY_SIZE(pxa25x_devices));
|
ARRAY_SIZE(pxa25x_devices));
|
||||||
|
@ -132,7 +132,8 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
|
|||||||
#ifndef CONFIG_IWMMXT
|
#ifndef CONFIG_IWMMXT
|
||||||
u64 acc0;
|
u64 acc0;
|
||||||
|
|
||||||
asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
|
asm volatile(".arch_extension xscale\n\t"
|
||||||
|
"mra %Q0, %R0, acc0" : "=r" (acc0));
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* ensure voltage-change sequencer not initiated, which hangs */
|
/* ensure voltage-change sequencer not initiated, which hangs */
|
||||||
@ -151,7 +152,8 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
|
|||||||
case PM_SUSPEND_MEM:
|
case PM_SUSPEND_MEM:
|
||||||
cpu_suspend(pwrmode, pxa27x_finish_suspend);
|
cpu_suspend(pwrmode, pxa27x_finish_suspend);
|
||||||
#ifndef CONFIG_IWMMXT
|
#ifndef CONFIG_IWMMXT
|
||||||
asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
|
asm volatile(".arch_extension xscale\n\t"
|
||||||
|
"mar acc0, %Q0, %R0" : "=r" (acc0));
|
||||||
#endif
|
#endif
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@ -309,7 +311,7 @@ static int __init pxa27x_init(void)
|
|||||||
if (!of_have_populated_dt()) {
|
if (!of_have_populated_dt()) {
|
||||||
pxa_register_device(&pxa27x_device_gpio,
|
pxa_register_device(&pxa27x_device_gpio,
|
||||||
&pxa27x_gpio_info);
|
&pxa27x_gpio_info);
|
||||||
pxa2xx_set_dmac_info(32);
|
pxa2xx_set_dmac_info(32, 75);
|
||||||
ret = platform_add_devices(devices,
|
ret = platform_add_devices(devices,
|
||||||
ARRAY_SIZE(devices));
|
ARRAY_SIZE(devices));
|
||||||
}
|
}
|
||||||
|
@ -68,7 +68,6 @@ static unsigned long wakeup_src;
|
|||||||
*/
|
*/
|
||||||
static void pxa3xx_cpu_standby(unsigned int pwrmode)
|
static void pxa3xx_cpu_standby(unsigned int pwrmode)
|
||||||
{
|
{
|
||||||
extern const char pm_enter_standby_start[], pm_enter_standby_end[];
|
|
||||||
void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
|
void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
|
||||||
|
|
||||||
memcpy_toio(sram + 0x8000, pm_enter_standby_start,
|
memcpy_toio(sram + 0x8000, pm_enter_standby_start,
|
||||||
@ -103,11 +102,10 @@ static void pxa3xx_cpu_pm_suspend(void)
|
|||||||
#ifndef CONFIG_IWMMXT
|
#ifndef CONFIG_IWMMXT
|
||||||
u64 acc0;
|
u64 acc0;
|
||||||
|
|
||||||
asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
|
asm volatile(".arch_extension xscale\n\t"
|
||||||
|
"mra %Q0, %R0, acc0" : "=r" (acc0));
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
extern int pxa3xx_finish_suspend(unsigned long);
|
|
||||||
|
|
||||||
/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
|
/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
|
||||||
CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
|
CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
|
||||||
CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
|
CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
|
||||||
@ -133,7 +131,8 @@ static void pxa3xx_cpu_pm_suspend(void)
|
|||||||
AD3ER = 0;
|
AD3ER = 0;
|
||||||
|
|
||||||
#ifndef CONFIG_IWMMXT
|
#ifndef CONFIG_IWMMXT
|
||||||
asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
|
asm volatile(".arch_extension xscale\n\t"
|
||||||
|
"mar acc0, %Q0, %R0" : "=r" (acc0));
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -450,7 +449,7 @@ static int __init pxa3xx_init(void)
|
|||||||
if (of_have_populated_dt())
|
if (of_have_populated_dt())
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
pxa2xx_set_dmac_info(32);
|
pxa2xx_set_dmac_info(32, 100);
|
||||||
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
|
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
@ -201,7 +201,7 @@ static void __init spitz_scoop_init(void)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* Power control is shared with between one of the CF slots and SD */
|
/* Power control is shared with between one of the CF slots and SD */
|
||||||
static void spitz_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)
|
static void __maybe_unused spitz_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)
|
||||||
{
|
{
|
||||||
unsigned short cpr;
|
unsigned short cpr;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
|
@ -910,7 +910,7 @@ static void __init zeus_map_io(void)
|
|||||||
PMCR = PSPR = 0;
|
PMCR = PSPR = 0;
|
||||||
|
|
||||||
/* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
|
/* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
|
||||||
OSCC |= OSCC_OON;
|
writel(readl(OSCC) | OSCC_OON, OSCC);
|
||||||
|
|
||||||
/* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
|
/* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
|
||||||
* float chip selects and PCMCIA */
|
* float chip selects and PCMCIA */
|
||||||
|
@ -190,7 +190,7 @@ DECLARE_IO(int,l,"")
|
|||||||
result; \
|
result; \
|
||||||
})
|
})
|
||||||
|
|
||||||
#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port)))
|
#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)0 + (port)))
|
||||||
|
|
||||||
#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
|
#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
|
||||||
#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
|
#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
|
||||||
|
@ -14,13 +14,6 @@
|
|||||||
#define __ASM_ARCH_MAP_H
|
#define __ASM_ARCH_MAP_H
|
||||||
|
|
||||||
#include <plat/map-base.h>
|
#include <plat/map-base.h>
|
||||||
|
|
||||||
/*
|
|
||||||
* S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
|
|
||||||
* So need to define it, and here is to avoid redefinition warning.
|
|
||||||
*/
|
|
||||||
#define S3C_UART_OFFSET (0x4000)
|
|
||||||
|
|
||||||
#include <plat/map-s3c.h>
|
#include <plat/map-s3c.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -34,9 +27,6 @@
|
|||||||
#define S3C2410_PA_MEMCTRL (0x48000000)
|
#define S3C2410_PA_MEMCTRL (0x48000000)
|
||||||
#define S3C24XX_SZ_MEMCTRL SZ_1M
|
#define S3C24XX_SZ_MEMCTRL SZ_1M
|
||||||
|
|
||||||
/* UARTs */
|
|
||||||
#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
|
|
||||||
|
|
||||||
/* Timers */
|
/* Timers */
|
||||||
#define S3C2410_PA_TIMER (0x51000000)
|
#define S3C2410_PA_TIMER (0x51000000)
|
||||||
#define S3C24XX_SZ_TIMER SZ_1M
|
#define S3C24XX_SZ_TIMER SZ_1M
|
||||||
@ -157,7 +147,6 @@
|
|||||||
|
|
||||||
#define S3C_PA_FB S3C2443_PA_FB
|
#define S3C_PA_FB S3C2443_PA_FB
|
||||||
#define S3C_PA_IIC S3C2410_PA_IIC
|
#define S3C_PA_IIC S3C2410_PA_IIC
|
||||||
#define S3C_PA_UART S3C24XX_PA_UART
|
|
||||||
#define S3C_PA_USBHOST S3C2410_PA_USBHOST
|
#define S3C_PA_USBHOST S3C2410_PA_USBHOST
|
||||||
#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0
|
#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0
|
||||||
#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC
|
#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC
|
||||||
|
@ -3,7 +3,8 @@
|
|||||||
#
|
#
|
||||||
# Licensed under GPLv2
|
# Licensed under GPLv2
|
||||||
menuconfig ARCH_S3C64XX
|
menuconfig ARCH_S3C64XX
|
||||||
bool "Samsung S3C64XX" if ARCH_MULTI_V6
|
bool "Samsung S3C64XX"
|
||||||
|
depends on ARCH_MULTI_V6
|
||||||
select ARCH_REQUIRE_GPIOLIB
|
select ARCH_REQUIRE_GPIOLIB
|
||||||
select ARM_AMBA
|
select ARM_AMBA
|
||||||
select ARM_VIC
|
select ARM_VIC
|
||||||
|
@ -6,28 +6,30 @@ config ARCH_SHMOBILE_MULTI
|
|||||||
|
|
||||||
config PM_RCAR
|
config PM_RCAR
|
||||||
bool
|
bool
|
||||||
select PM_GENERIC_DOMAINS if PM
|
select PM
|
||||||
|
select PM_GENERIC_DOMAINS
|
||||||
|
|
||||||
config PM_RMOBILE
|
config PM_RMOBILE
|
||||||
bool
|
bool
|
||||||
|
select PM
|
||||||
select PM_GENERIC_DOMAINS
|
select PM_GENERIC_DOMAINS
|
||||||
|
|
||||||
config ARCH_RCAR_GEN1
|
config ARCH_RCAR_GEN1
|
||||||
bool
|
bool
|
||||||
select PM_RCAR if PM || SMP
|
select PM_RCAR
|
||||||
select RENESAS_INTC_IRQPIN
|
select RENESAS_INTC_IRQPIN
|
||||||
select SYS_SUPPORTS_SH_TMU
|
select SYS_SUPPORTS_SH_TMU
|
||||||
|
|
||||||
config ARCH_RCAR_GEN2
|
config ARCH_RCAR_GEN2
|
||||||
bool
|
bool
|
||||||
select PM_RCAR if PM || SMP
|
select PM_RCAR
|
||||||
select RENESAS_IRQC
|
select RENESAS_IRQC
|
||||||
select SYS_SUPPORTS_SH_CMT
|
select SYS_SUPPORTS_SH_CMT
|
||||||
select PCI_DOMAINS if PCI
|
select PCI_DOMAINS if PCI
|
||||||
|
|
||||||
config ARCH_RMOBILE
|
config ARCH_RMOBILE
|
||||||
bool
|
bool
|
||||||
select PM_RMOBILE if PM
|
select PM_RMOBILE
|
||||||
select SYS_SUPPORTS_SH_CMT
|
select SYS_SUPPORTS_SH_CMT
|
||||||
select SYS_SUPPORTS_SH_TMU
|
select SYS_SUPPORTS_SH_TMU
|
||||||
|
|
||||||
@ -55,7 +57,8 @@ config ARCH_EMEV2
|
|||||||
|
|
||||||
config ARCH_R7S72100
|
config ARCH_R7S72100
|
||||||
bool "RZ/A1H (R7S72100)"
|
bool "RZ/A1H (R7S72100)"
|
||||||
select PM_GENERIC_DOMAINS if PM
|
select PM
|
||||||
|
select PM_GENERIC_DOMAINS
|
||||||
select SYS_SUPPORTS_SH_MTU2
|
select SYS_SUPPORTS_SH_MTU2
|
||||||
|
|
||||||
config ARCH_R8A73A4
|
config ARCH_R8A73A4
|
||||||
|
6
arch/arm/mach-shmobile/emev2.h
Normal file
6
arch/arm/mach-shmobile/emev2.h
Normal file
@ -0,0 +1,6 @@
|
|||||||
|
#ifndef __ASM_EMEV2_H__
|
||||||
|
#define __ASM_EMEV2_H__
|
||||||
|
|
||||||
|
extern const struct smp_operations emev2_smp_ops;
|
||||||
|
|
||||||
|
#endif /* __ASM_EMEV2_H__ */
|
@ -18,35 +18,17 @@
|
|||||||
#include <asm/mach-types.h>
|
#include <asm/mach-types.h>
|
||||||
#include <asm/mach/arch.h>
|
#include <asm/mach/arch.h>
|
||||||
#include <asm/mach/map.h>
|
#include <asm/mach/map.h>
|
||||||
|
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
|
#include "emev2.h"
|
||||||
static struct map_desc emev2_io_desc[] __initdata = {
|
|
||||||
#ifdef CONFIG_SMP
|
|
||||||
/* 2M mapping for SCU + L2 controller */
|
|
||||||
{
|
|
||||||
.virtual = 0xf0000000,
|
|
||||||
.pfn = __phys_to_pfn(0x1e000000),
|
|
||||||
.length = SZ_2M,
|
|
||||||
.type = MT_DEVICE
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init emev2_map_io(void)
|
|
||||||
{
|
|
||||||
iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
|
|
||||||
}
|
|
||||||
|
|
||||||
static const char *const emev2_boards_compat_dt[] __initconst = {
|
static const char *const emev2_boards_compat_dt[] __initconst = {
|
||||||
"renesas,emev2",
|
"renesas,emev2",
|
||||||
NULL,
|
NULL,
|
||||||
};
|
};
|
||||||
|
|
||||||
extern const struct smp_operations emev2_smp_ops;
|
|
||||||
|
|
||||||
DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
|
DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
|
||||||
.smp = smp_ops(emev2_smp_ops),
|
.smp = smp_ops(emev2_smp_ops),
|
||||||
.map_io = emev2_map_io,
|
|
||||||
.init_early = shmobile_init_delay,
|
.init_early = shmobile_init_delay,
|
||||||
.init_late = shmobile_init_late,
|
.init_late = shmobile_init_late,
|
||||||
.dt_compat = emev2_boards_compat_dt,
|
.dt_compat = emev2_boards_compat_dt,
|
||||||
|
@ -23,41 +23,9 @@
|
|||||||
#include <asm/mach/map.h>
|
#include <asm/mach/map.h>
|
||||||
#include <asm/mach/arch.h>
|
#include <asm/mach/arch.h>
|
||||||
#include <asm/mach/time.h>
|
#include <asm/mach/time.h>
|
||||||
#include <asm/hardware/cache-l2x0.h>
|
|
||||||
|
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
|
|
||||||
static struct map_desc r8a7740_io_desc[] __initdata = {
|
|
||||||
/*
|
|
||||||
* for CPGA/INTC/PFC
|
|
||||||
* 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
|
|
||||||
*/
|
|
||||||
{
|
|
||||||
.virtual = 0xe6000000,
|
|
||||||
.pfn = __phys_to_pfn(0xe6000000),
|
|
||||||
.length = 160 << 20,
|
|
||||||
.type = MT_DEVICE_NONSHARED
|
|
||||||
},
|
|
||||||
#ifdef CONFIG_CACHE_L2X0
|
|
||||||
/*
|
|
||||||
* for l2x0_init()
|
|
||||||
* 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
|
|
||||||
*/
|
|
||||||
{
|
|
||||||
.virtual = 0xf0002000,
|
|
||||||
.pfn = __phys_to_pfn(0xf0100000),
|
|
||||||
.length = PAGE_SIZE,
|
|
||||||
.type = MT_DEVICE_NONSHARED
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init r8a7740_map_io(void)
|
|
||||||
{
|
|
||||||
debug_ll_io_init();
|
|
||||||
iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* r8a7740 chip has lasting errata on MERAM buffer.
|
* r8a7740 chip has lasting errata on MERAM buffer.
|
||||||
* this is work-around for it.
|
* this is work-around for it.
|
||||||
@ -110,10 +78,6 @@ static void __init r8a7740_generic_init(void)
|
|||||||
{
|
{
|
||||||
r8a7740_meram_workaround();
|
r8a7740_meram_workaround();
|
||||||
|
|
||||||
#ifdef CONFIG_CACHE_L2X0
|
|
||||||
/* Shared attribute override enable, 32K*8way */
|
|
||||||
l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
|
|
||||||
#endif
|
|
||||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -123,7 +87,8 @@ static const char *const r8a7740_boards_compat_dt[] __initconst = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
|
DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
|
||||||
.map_io = r8a7740_map_io,
|
.l2c_aux_val = 0,
|
||||||
|
.l2c_aux_mask = ~0,
|
||||||
.init_early = shmobile_init_delay,
|
.init_early = shmobile_init_delay,
|
||||||
.init_irq = r8a7740_init_irq_of,
|
.init_irq = r8a7740_init_irq_of,
|
||||||
.init_machine = r8a7740_generic_init,
|
.init_machine = r8a7740_generic_init,
|
||||||
|
@ -21,7 +21,9 @@
|
|||||||
#include <linux/delay.h>
|
#include <linux/delay.h>
|
||||||
#include <asm/smp_plat.h>
|
#include <asm/smp_plat.h>
|
||||||
#include <asm/smp_scu.h>
|
#include <asm/smp_scu.h>
|
||||||
|
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
|
#include "emev2.h"
|
||||||
|
|
||||||
#define EMEV2_SCU_BASE 0x1e000000
|
#define EMEV2_SCU_BASE 0x1e000000
|
||||||
#define EMEV2_SMU_BASE 0xe0110000
|
#define EMEV2_SMU_BASE 0xe0110000
|
||||||
|
@ -10,6 +10,7 @@
|
|||||||
|
|
||||||
static const char *const stm32_compat[] __initconst = {
|
static const char *const stm32_compat[] __initconst = {
|
||||||
"st,stm32f429",
|
"st,stm32f429",
|
||||||
|
"st,stm32f469",
|
||||||
NULL
|
NULL
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -69,6 +69,7 @@ MACHINE_END
|
|||||||
static const char * const sun8i_board_dt_compat[] = {
|
static const char * const sun8i_board_dt_compat[] = {
|
||||||
"allwinner,sun8i-a23",
|
"allwinner,sun8i-a23",
|
||||||
"allwinner,sun8i-a33",
|
"allwinner,sun8i-a33",
|
||||||
|
"allwinner,sun8i-a83t",
|
||||||
"allwinner,sun8i-h3",
|
"allwinner,sun8i-h3",
|
||||||
NULL,
|
NULL,
|
||||||
};
|
};
|
||||||
|
@ -30,7 +30,7 @@
|
|||||||
* The secondary CPUs check this register from the boot ROM for the jump
|
* The secondary CPUs check this register from the boot ROM for the jump
|
||||||
* destination. After that, it can be reused as a scratch register.
|
* destination. After that, it can be reused as a scratch register.
|
||||||
*/
|
*/
|
||||||
#define UNIPHIER_SBC_ROM_BOOT_RSV2 0x1208
|
#define UNIPHIER_SMPCTRL_ROM_RSV2 0x208
|
||||||
|
|
||||||
static void __iomem *uniphier_smp_rom_boot_rsv2;
|
static void __iomem *uniphier_smp_rom_boot_rsv2;
|
||||||
static unsigned int uniphier_smp_max_cpus;
|
static unsigned int uniphier_smp_max_cpus;
|
||||||
@ -98,16 +98,24 @@ static int __init uniphier_smp_prepare_trampoline(unsigned int max_cpus)
|
|||||||
phys_addr_t rom_rsv2_phys;
|
phys_addr_t rom_rsv2_phys;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
np = of_find_compatible_node(NULL, NULL,
|
np = of_find_compatible_node(NULL, NULL, "socionext,uniphier-smpctrl");
|
||||||
"socionext,uniphier-system-bus-controller");
|
of_node_put(np);
|
||||||
ret = of_address_to_resource(np, 1, &res);
|
ret = of_address_to_resource(np, 0, &res);
|
||||||
if (ret) {
|
if (!ret) {
|
||||||
pr_err("failed to get resource of system-bus-controller\n");
|
rom_rsv2_phys = res.start + UNIPHIER_SMPCTRL_ROM_RSV2;
|
||||||
return ret;
|
} else {
|
||||||
|
/* try old binding too */
|
||||||
|
np = of_find_compatible_node(NULL, NULL,
|
||||||
|
"socionext,uniphier-system-bus-controller");
|
||||||
|
of_node_put(np);
|
||||||
|
ret = of_address_to_resource(np, 1, &res);
|
||||||
|
if (ret) {
|
||||||
|
pr_err("failed to get resource of SMP control\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
rom_rsv2_phys = res.start + 0x1000 + UNIPHIER_SMPCTRL_ROM_RSV2;
|
||||||
}
|
}
|
||||||
|
|
||||||
rom_rsv2_phys = res.start + UNIPHIER_SBC_ROM_BOOT_RSV2;
|
|
||||||
|
|
||||||
ret = uniphier_smp_copy_trampoline(rom_rsv2_phys);
|
ret = uniphier_smp_copy_trampoline(rom_rsv2_phys);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user