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clk: meson8b: fix clk81 register address

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During meson8b clock probe, clk81 register address is fixed twice.
First using the meson8b_clk_gates array, then by directly changing
meson8b_clk81 register.

As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base.

Fixed by just removing the second fixup.

Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Jerome Brunet 2017-01-25 11:53:06 +01:00 committed by Stephen Boyd
parent 88c9b70bb2
commit 340a84ce1e
1 changed files with 0 additions and 1 deletions
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drivers/clk/meson/meson8b.c
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@ -607,7 +607,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
/* Populate the base address for the MPEG clks */ /* Populate the base address for the MPEG clks */
meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg; meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg;
meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg; meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
/* Populate base address for gates */ /* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++) for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)