powerpc/64s: Convert some cpu_setup() and cpu_restore() functions to C
The only thing keeping the cpu_setup() and cpu_restore() functions
used in the cputable entries for Power7, Power8, Power9 and Power10 in
assembly was cpu_restore() being called before there was a stack in
generic_secondary_smp_init(). Commit ("powerpc/64: Set up a kernel
stack for secondaries before cpu_restore()") means that it is now
possible to use C.
Rewrite the functions in C so they are a little bit easier to read.
This is not changing their functionality.
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
[mpe: Tweak copyright and authorship notes]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201014072837.24539-2-jniethe5@gmail.com
This commit is contained in:
Jordan Niethe
Michael Ellerman
parent
3c0b976bf2
commit
344fbab991
12
arch/powerpc/include/asm/cpu_setup_power.h
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12
arch/powerpc/include/asm/cpu_setup_power.h
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2020 IBM Corporation
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*/
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void __setup_cpu_power7(unsigned long offset, struct cpu_spec *spec);
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void __restore_cpu_power7(void);
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void __setup_cpu_power8(unsigned long offset, struct cpu_spec *spec);
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void __restore_cpu_power8(void);
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void __setup_cpu_power9(unsigned long offset, struct cpu_spec *spec);
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void __restore_cpu_power9(void);
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void __setup_cpu_power10(unsigned long offset, struct cpu_spec *spec);
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void __restore_cpu_power10(void);
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@ -1,252 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This file contains low level CPU setup functions.
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* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*/
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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#include <asm/book3s/64/mmu-hash.h>
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/* Entry: r3 = crap, r4 = ptr to cputable entry
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*
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* Note that we can be called twice for pseudo-PVRs
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*/
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_GLOBAL(__setup_cpu_power7)
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mflr r11
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bl __init_hvmode_206
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
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bl __init_LPCR_ISA206
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mtlr r11
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blr
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_GLOBAL(__restore_cpu_power7)
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mflr r11
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mfmsr r3
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rldicl. r0,r3,4,63
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
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bl __init_LPCR_ISA206
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mtlr r11
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blr
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_GLOBAL(__setup_cpu_power8)
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mflr r11
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bl __init_FSCR
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bl __init_PMU
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bl __init_PMU_ISA207
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bl __init_hvmode_206
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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ori r3, r3, LPCR_PECEDH
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li r4,0 /* LPES = 0 */
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bl __init_LPCR_ISA206
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bl __init_HFSCR
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bl __init_PMU_HV
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bl __init_PMU_HV_ISA207
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mtlr r11
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blr
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_GLOBAL(__restore_cpu_power8)
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mflr r11
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bl __init_FSCR
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bl __init_PMU
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bl __init_PMU_ISA207
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mfmsr r3
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rldicl. r0,r3,4,63
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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ori r3, r3, LPCR_PECEDH
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li r4,0 /* LPES = 0 */
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bl __init_LPCR_ISA206
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bl __init_HFSCR
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bl __init_PMU_HV
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bl __init_PMU_HV_ISA207
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mtlr r11
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blr
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_GLOBAL(__setup_cpu_power10)
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mflr r11
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bl __init_FSCR_power10
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bl __init_PMU
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bl __init_PMU_ISA31
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b 1f
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_GLOBAL(__setup_cpu_power9)
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mflr r11
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bl __init_FSCR_power9
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bl __init_PMU
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1: bl __init_hvmode_206
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_PSSCR,r0
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mtspr SPRN_LPID,r0
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mtspr SPRN_PID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
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or r3, r3, r4
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LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
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andc r3, r3, r4
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li r4,0 /* LPES = 0 */
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bl __init_LPCR_ISA300
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bl __init_HFSCR
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bl __init_PMU_HV
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mtlr r11
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blr
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_GLOBAL(__restore_cpu_power10)
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mflr r11
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bl __init_FSCR_power10
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bl __init_PMU
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bl __init_PMU_ISA31
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b 1f
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_GLOBAL(__restore_cpu_power9)
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mflr r11
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bl __init_FSCR_power9
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bl __init_PMU
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1: mfmsr r3
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rldicl. r0,r3,4,63
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_PSSCR,r0
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mtspr SPRN_LPID,r0
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mtspr SPRN_PID,r0
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LOAD_REG_IMMEDIATE(r0, PCR_MASK)
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mtspr SPRN_PCR,r0
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mfspr r3,SPRN_LPCR
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LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
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or r3, r3, r4
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LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
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andc r3, r3, r4
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li r4,0 /* LPES = 0 */
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bl __init_LPCR_ISA300
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bl __init_HFSCR
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bl __init_PMU_HV
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mtlr r11
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blr
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__init_hvmode_206:
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/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
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mfmsr r3
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rldicl. r0,r3,4,63
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bnelr
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ld r5,CPU_SPEC_FEATURES(r4)
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LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST)
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andc r5,r5,r6
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std r5,CPU_SPEC_FEATURES(r4)
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blr
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__init_LPCR_ISA206:
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/* Setup a sane LPCR:
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* Called with initial LPCR in R3 and desired LPES 2-bit value in R4
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*
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* LPES = 0b01 (HSRR0/1 used for 0x500)
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* PECE = 0b111
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* DPFD = 4
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* HDICE = 0
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* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
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* VRMASD = 0b10000 (L=1, LP=00)
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*
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* Other bits untouched for now
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*/
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li r5,0x10
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rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
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/* POWER9 has no VRMASD */
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__init_LPCR_ISA300:
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rldimi r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
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ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
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li r5,4
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rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
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clrrdi r3,r3,1 /* clear HDICE */
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li r5,4
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rldimi r3,r5, LPCR_VC_SH, 0
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mtspr SPRN_LPCR,r3
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isync
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blr
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__init_FSCR_power10:
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mfspr r3, SPRN_FSCR
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ori r3, r3, FSCR_PREFIX
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mtspr SPRN_FSCR, r3
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// fall through
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__init_FSCR_power9:
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mfspr r3, SPRN_FSCR
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ori r3, r3, FSCR_SCV
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mtspr SPRN_FSCR, r3
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// fall through
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__init_FSCR:
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mfspr r3,SPRN_FSCR
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ori r3,r3,FSCR_TAR|FSCR_EBB
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mtspr SPRN_FSCR,r3
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blr
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__init_HFSCR:
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mfspr r3,SPRN_HFSCR
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ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
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HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
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mtspr SPRN_HFSCR,r3
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blr
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__init_PMU_HV:
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li r5,0
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mtspr SPRN_MMCRC,r5
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blr
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__init_PMU_HV_ISA207:
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li r5,0
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mtspr SPRN_MMCRH,r5
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blr
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__init_PMU:
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li r5,0
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mtspr SPRN_MMCRA,r5
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mtspr SPRN_MMCR0,r5
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mtspr SPRN_MMCR1,r5
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mtspr SPRN_MMCR2,r5
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blr
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__init_PMU_ISA207:
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li r5,0
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mtspr SPRN_MMCRS,r5
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blr
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__init_PMU_ISA31:
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li r5,0
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mtspr SPRN_MMCR3,r5
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LOAD_REG_IMMEDIATE(r5, MMCRA_BHRB_DISABLE)
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mtspr SPRN_MMCRA,r5
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blr
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271
arch/powerpc/kernel/cpu_setup_power.c
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271
arch/powerpc/kernel/cpu_setup_power.c
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@ -0,0 +1,271 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2020, Jordan Niethe, IBM Corporation.
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*
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* This file contains low level CPU setup functions.
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* Originally written in assembly by Benjamin Herrenschmidt & various other
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* authors.
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*/
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#include <asm/reg.h>
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#include <asm/synch.h>
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#include <linux/bitops.h>
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#include <asm/cputable.h>
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#include <asm/cpu_setup_power.h>
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/* Disable CPU_FTR_HVMODE and return false if MSR:HV is not set */
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static bool init_hvmode_206(struct cpu_spec *t)
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{
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u64 msr;
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msr = mfmsr();
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if (msr & MSR_HV)
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return true;
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t->cpu_features &= ~(CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST);
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return false;
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}
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static void init_LPCR_ISA300(u64 lpcr, u64 lpes)
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{
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/* POWER9 has no VRMASD */
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lpcr |= (lpes << LPCR_LPES_SH) & LPCR_LPES;
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lpcr |= LPCR_PECE0|LPCR_PECE1|LPCR_PECE2;
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lpcr |= (4ull << LPCR_DPFD_SH) & LPCR_DPFD;
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lpcr &= ~LPCR_HDICE; /* clear HDICE */
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lpcr |= (4ull << LPCR_VC_SH);
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mtspr(SPRN_LPCR, lpcr);
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isync();
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}
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/*
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* Setup a sane LPCR:
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* Called with initial LPCR and desired LPES 2-bit value
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*
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* LPES = 0b01 (HSRR0/1 used for 0x500)
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* PECE = 0b111
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* DPFD = 4
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* HDICE = 0
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* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
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* VRMASD = 0b10000 (L=1, LP=00)
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*
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* Other bits untouched for now
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*/
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static void init_LPCR_ISA206(u64 lpcr, u64 lpes)
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{
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lpcr |= (0x10ull << LPCR_VRMASD_SH) & LPCR_VRMASD;
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init_LPCR_ISA300(lpcr, lpes);
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}
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static void init_FSCR(void)
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{
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u64 fscr;
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fscr = mfspr(SPRN_FSCR);
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fscr |= FSCR_TAR|FSCR_EBB;
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mtspr(SPRN_FSCR, fscr);
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}
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static void init_FSCR_power9(void)
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{
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u64 fscr;
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fscr = mfspr(SPRN_FSCR);
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fscr |= FSCR_SCV;
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mtspr(SPRN_FSCR, fscr);
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init_FSCR();
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}
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static void init_FSCR_power10(void)
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{
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u64 fscr;
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fscr = mfspr(SPRN_FSCR);
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fscr |= FSCR_PREFIX;
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mtspr(SPRN_FSCR, fscr);
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init_FSCR_power9();
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}
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static void init_HFSCR(void)
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{
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u64 hfscr;
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hfscr = mfspr(SPRN_HFSCR);
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hfscr |= HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|HFSCR_DSCR|\
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HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP;
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mtspr(SPRN_HFSCR, hfscr);
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}
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static void init_PMU_HV(void)
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{
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mtspr(SPRN_MMCRC, 0);
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}
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static void init_PMU_HV_ISA207(void)
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{
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mtspr(SPRN_MMCRH, 0);
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}
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static void init_PMU(void)
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{
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mtspr(SPRN_MMCRA, 0);
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mtspr(SPRN_MMCR0, 0);
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mtspr(SPRN_MMCR1, 0);
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mtspr(SPRN_MMCR2, 0);
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}
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static void init_PMU_ISA207(void)
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{
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mtspr(SPRN_MMCRS, 0);
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}
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static void init_PMU_ISA31(void)
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{
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mtspr(SPRN_MMCR3, 0);
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mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
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}
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/*
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* Note that we can be called twice of pseudo-PVRs.
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* The parameter offset is not used.
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*/
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void __setup_cpu_power7(unsigned long offset, struct cpu_spec *t)
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{
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if (!init_hvmode_206(t))
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return;
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mtspr(SPRN_LPID, 0);
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mtspr(SPRN_PCR, PCR_MASK);
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init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH);
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}
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void __restore_cpu_power7(void)
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{
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u64 msr;
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msr = mfmsr();
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if (!(msr & MSR_HV))
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return;
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mtspr(SPRN_LPID, 0);
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mtspr(SPRN_PCR, PCR_MASK);
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init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH);
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}
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void __setup_cpu_power8(unsigned long offset, struct cpu_spec *t)
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{
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init_FSCR();
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init_PMU();
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init_PMU_ISA207();
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if (!init_hvmode_206(t))
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return;
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mtspr(SPRN_LPID, 0);
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mtspr(SPRN_PCR, PCR_MASK);
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init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */
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init_HFSCR();
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init_PMU_HV();
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init_PMU_HV_ISA207();
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}
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void __restore_cpu_power8(void)
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{
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u64 msr;
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init_FSCR();
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init_PMU();
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init_PMU_ISA207();
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msr = mfmsr();
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if (!(msr & MSR_HV))
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return;
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mtspr(SPRN_LPID, 0);
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||||
mtspr(SPRN_PCR, PCR_MASK);
|
||||
init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */
|
||||
init_HFSCR();
|
||||
init_PMU_HV();
|
||||
init_PMU_HV_ISA207();
|
||||
}
|
||||
|
||||
void __setup_cpu_power9(unsigned long offset, struct cpu_spec *t)
|
||||
{
|
||||
init_FSCR_power9();
|
||||
init_PMU();
|
||||
|
||||
if (!init_hvmode_206(t))
|
||||
return;
|
||||
|
||||
mtspr(SPRN_PSSCR, 0);
|
||||
mtspr(SPRN_LPID, 0);
|
||||
mtspr(SPRN_PID, 0);
|
||||
mtspr(SPRN_PCR, PCR_MASK);
|
||||
init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
|
||||
LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
|
||||
init_HFSCR();
|
||||
init_PMU_HV();
|
||||
}
|
||||
|
||||
void __restore_cpu_power9(void)
|
||||
{
|
||||
u64 msr;
|
||||
|
||||
init_FSCR_power9();
|
||||
init_PMU();
|
||||
|
||||
msr = mfmsr();
|
||||
if (!(msr & MSR_HV))
|
||||
return;
|
||||
|
||||
mtspr(SPRN_PSSCR, 0);
|
||||
mtspr(SPRN_LPID, 0);
|
||||
mtspr(SPRN_PID, 0);
|
||||
mtspr(SPRN_PCR, PCR_MASK);
|
||||
init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
|
||||
LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
|
||||
init_HFSCR();
|
||||
init_PMU_HV();
|
||||
}
|
||||
|
||||
void __setup_cpu_power10(unsigned long offset, struct cpu_spec *t)
|
||||
{
|
||||
init_FSCR_power10();
|
||||
init_PMU();
|
||||
init_PMU_ISA31();
|
||||
|
||||
if (!init_hvmode_206(t))
|
||||
return;
|
||||
|
||||
mtspr(SPRN_PSSCR, 0);
|
||||
mtspr(SPRN_LPID, 0);
|
||||
mtspr(SPRN_PID, 0);
|
||||
mtspr(SPRN_PCR, PCR_MASK);
|
||||
init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
|
||||
LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
|
||||
init_HFSCR();
|
||||
init_PMU_HV();
|
||||
}
|
||||
|
||||
void __restore_cpu_power10(void)
|
||||
{
|
||||
u64 msr;
|
||||
|
||||
init_FSCR_power10();
|
||||
init_PMU();
|
||||
init_PMU_ISA31();
|
||||
|
||||
msr = mfmsr();
|
||||
if (!(msr & MSR_HV))
|
||||
return;
|
||||
|
||||
mtspr(SPRN_PSSCR, 0);
|
||||
mtspr(SPRN_LPID, 0);
|
||||
mtspr(SPRN_PID, 0);
|
||||
mtspr(SPRN_PCR, PCR_MASK);
|
||||
init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
|
||||
LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
|
||||
init_HFSCR();
|
||||
init_PMU_HV();
|
||||
}
|
||||
@ -60,19 +60,15 @@ extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
|
||||
#endif /* CONFIG_PPC32 */
|
||||
#ifdef CONFIG_PPC64
|
||||
#include <asm/cpu_setup_power.h>
|
||||
extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __restore_cpu_pa6t(void);
|
||||
extern void __restore_cpu_ppc970(void);
|
||||
extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __restore_cpu_power7(void);
|
||||
extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __restore_cpu_power8(void);
|
||||
extern void __setup_cpu_power9(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __restore_cpu_power9(void);
|
||||
extern void __setup_cpu_power10(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __restore_cpu_power10(void);
|
||||
extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
|
||||
extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
|
||||
extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
|
||||
#endif /* CONFIG_PPC64 */
|
||||
#if defined(CONFIG_E500)
|
||||
extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user