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arm64: dts: freescale: Add missing cooling device properties for CPUs

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The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.

Add such missing properties.

Do minor rearrangement as well to keep ordering consistent.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Viresh Kumar 2018-05-25 11:10:02 +05:30 committed by Shawn Guo
parent 7a2aeb9175
commit 346f5976cc
5 changed files with 21 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -43,8 +43,8 @@
reg = <0x0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
@ -54,6 +54,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
cpu2: cpu@2 {
@ -63,6 +64,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
cpu3: cpu@3 {
@ -72,6 +74,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
l2: l2-cache {

3
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -50,6 +50,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
cpu2: cpu@2 {
@ -59,6 +60,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
cpu3: cpu@3 {
@ -68,6 +70,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
l2: l2-cache {

6
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -40,6 +40,7 @@
reg = <0x1>;
clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
cpu2: cpu@2 {
@ -48,6 +49,7 @@
reg = <0x2>;
clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
cpu3: cpu@3 {
@ -56,6 +58,7 @@
reg = <0x3>;
clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
cpu4: cpu@100 {
@ -73,6 +76,7 @@
reg = <0x101>;
clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
cpu6: cpu@102 {
@ -81,6 +85,7 @@
reg = <0x102>;
clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
cpu7: cpu@103 {
@ -89,6 +94,7 @@
reg = <0x103>;
clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>;
};
CPU_PH20: cpu-ph20 {

4
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View File

@ -29,6 +29,7 @@
clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>;
};
cpu2: cpu@100 {
@ -48,6 +49,7 @@
clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>;
};
cpu4: cpu@200 {
@ -67,6 +69,7 @@
clocks = <&clockgen 1 2>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>;
#cooling-cells = <2>;
};
cpu6: cpu@300 {
@ -86,6 +89,7 @@
clocks = <&clockgen 1 3>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>;
#cooling-cells = <2>;
};
cluster0_l2: l2-cache0 {

4
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
View File

@ -29,6 +29,7 @@
clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>;
};
cpu2: cpu@100 {
@ -48,6 +49,7 @@
clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>;
};
cpu4: cpu@200 {
@ -67,6 +69,7 @@
clocks = <&clockgen 1 2>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>;
#cooling-cells = <2>;
};
cpu6: cpu@300 {
@ -86,6 +89,7 @@
clocks = <&clockgen 1 3>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>;
#cooling-cells = <2>;
};
cluster0_l2: l2-cache0 {