perf/x86/intel: Factor out intel_pmu_check_extra_regs
Each Hybrid PMU has to check and update its own extra registers before registration. The intel_pmu_check_extra_regs will be reused later to check the extra registers of each hybrid PMU. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/1618237865-33448-14-git-send-email-kan.liang@linux.intel.com
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Peter Zijlstra
parent
bc14fe1bee
commit
34d5b61f29
@ -5127,6 +5127,26 @@ static void intel_pmu_check_event_constraints(struct event_constraint *event_con
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}
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}
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}
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}
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static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
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{
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struct extra_reg *er;
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/*
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* Access extra MSR may cause #GP under certain circumstances.
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* E.g. KVM doesn't support offcore event
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* Check all extra_regs here.
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*/
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if (!extra_regs)
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return;
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for (er = extra_regs; er->msr; er++) {
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er->extra_msr_access = check_msr(er->msr, 0x11UL);
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/* Disable LBR select mapping */
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if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
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x86_pmu.lbr_sel_map = NULL;
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}
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}
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__init int intel_pmu_init(void)
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__init int intel_pmu_init(void)
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{
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{
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struct attribute **extra_skl_attr = &empty_attrs;
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struct attribute **extra_skl_attr = &empty_attrs;
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@ -5138,7 +5158,6 @@ __init int intel_pmu_init(void)
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union cpuid10_eax eax;
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union cpuid10_eax eax;
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union cpuid10_ebx ebx;
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union cpuid10_ebx ebx;
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unsigned int fixed_mask;
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unsigned int fixed_mask;
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struct extra_reg *er;
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bool pmem = false;
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bool pmem = false;
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int version, i;
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int version, i;
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char *name;
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char *name;
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@ -5795,19 +5814,7 @@ __init int intel_pmu_init(void)
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if (x86_pmu.lbr_nr)
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if (x86_pmu.lbr_nr)
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pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
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pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
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/*
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intel_pmu_check_extra_regs(x86_pmu.extra_regs);
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* Access extra MSR may cause #GP under certain circumstances.
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* E.g. KVM doesn't support offcore event
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* Check all extra_regs here.
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*/
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if (x86_pmu.extra_regs) {
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for (er = x86_pmu.extra_regs; er->msr; er++) {
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er->extra_msr_access = check_msr(er->msr, 0x11UL);
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/* Disable LBR select mapping */
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if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
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x86_pmu.lbr_sel_map = NULL;
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}
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}
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/* Support full width counters using alternative MSR range */
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/* Support full width counters using alternative MSR range */
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if (x86_pmu.intel_cap.full_width_write) {
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if (x86_pmu.intel_cap.full_width_write) {
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