Merge tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul:
"This time we have aded a new capability for scatter-gathered memset
using dmaengine APIs. This is supported in xdmac & hdmac drivers
We have added support for reusing descriptors for examples like video
buffers etc. Driver will follow
The behaviour of descriptor ack has been clarified and documented
New devices added are:
- dma controller in sun[457]i SoCs
- lpc18xx dmamux
- ZTE ZX296702 dma controller
- Analog Devices AXI-DMAC DMA controller
- eDMA support for dma-crossbar
- imx6sx support in imx-sdma driver
- imx-sdma device to device support
Other:
- jz4780 fixes
- ioatdma large refactor and cleanup for removal of ioat v1 and v2
which is deprecated and fixes
- ACPI support in X-Gene DMA engine driver
- ipu irq fixes
- mvxor fixes
- minor fixes spread thru drivers"
[ The Kconfig and Makefile entries got re-sorted alphabetically, and I
handled the conflict with the new Intel integrated IDMA driver by
slightly mis-sorting it on purpose: "IDMA64" got sorted after "IMX" in
order to keep the Intel entries together. I think it might be a good
idea to just rename the IDMA64 config entry to INTEL_IDMA64 to make
the sorting be a true sort, not this mismash.
Also, this merge disables the COMPILE_TEST for the sun4i DMA
controller, because it does not compile cleanly at all. - Linus ]
* tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (89 commits)
dmaengine: ioatdma: add Broadwell EP ioatdma PCI dev IDs
dmaengine :ipu: change ipu_irq_handler() to remove compile warning
dmaengine: ioatdma: Fix variable array length
dmaengine: ioatdma: fix sparse "error" with prep lock
dmaengine: hdmac: Add memset capabilities
dmaengine: sort the sh Makefile
dmaengine: sort the sh Kconfig
dmaengine: sort the dw Kconfig
dmaengine: sort the Kconfig
dmaengine: sort the makefile
drivers/dma: make mv_xor.c driver explicitly non-modular
dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller
devicetree: Add bindings documentation for Analog Devices AXI-DMAC
dmaengine: xgene-dma: Fix the lock to allow client for further submission of requests
dmaengine: ioatdma: fix coccinelle warning
dmaengine: ioatdma: fix zero day warning on incompatible pointer type
dmaengine: tegra-apb: Simplify locking for device using global pause
dmaengine: tegra-apb: Remove unnecessary return statements and variables
dmaengine: tegra-apb: Avoid unnecessary channel base address calculation
dmaengine: tegra-apb: Remove unused variables
...
This commit is contained in:
Linus Torvalds
@ -625,12 +625,12 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
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struct at_xdmac_desc *first = NULL, *prev = NULL;
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struct scatterlist *sg;
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int i;
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unsigned int xfer_size = 0;
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unsigned long irqflags;
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struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
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struct at_xdmac_desc *first = NULL, *prev = NULL;
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struct scatterlist *sg;
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int i;
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unsigned int xfer_size = 0;
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unsigned long irqflags;
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struct dma_async_tx_descriptor *ret = NULL;
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if (!sgl)
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@ -797,10 +797,7 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
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list_add_tail(&desc->desc_node, &first->descs_list);
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}
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prev->lld.mbr_nda = first->tx_dma_desc.phys;
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dev_dbg(chan2dev(chan),
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"%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
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__func__, prev, &prev->lld.mbr_nda);
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at_xdmac_queue_desc(chan, prev, first);
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first->tx_dma_desc.flags = flags;
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first->xfer_size = buf_len;
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first->direction = direction;
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@ -1135,7 +1132,7 @@ static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
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* SAMA5D4x), so we can use the same interface for source and dest,
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* that solves the fact we don't know the direction.
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*/
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u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
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u32 chan_cc = AT_XDMAC_CC_DAM_UBS_AM
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| AT_XDMAC_CC_SAM_INCREMENTED_AM
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| AT_XDMAC_CC_DIF(0)
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| AT_XDMAC_CC_SIF(0)
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@ -1203,6 +1200,168 @@ at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
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return &desc->tx_dma_desc;
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}
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static struct dma_async_tx_descriptor *
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at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, int value,
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unsigned long flags)
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{
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struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
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struct at_xdmac_desc *desc, *pdesc = NULL,
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*ppdesc = NULL, *first = NULL;
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struct scatterlist *sg, *psg = NULL, *ppsg = NULL;
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size_t stride = 0, pstride = 0, len = 0;
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int i;
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if (!sgl)
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return NULL;
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dev_dbg(chan2dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n",
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__func__, sg_len, value, flags);
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/* Prepare descriptors. */
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for_each_sg(sgl, sg, sg_len, i) {
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dev_dbg(chan2dev(chan), "%s: dest=0x%08x, len=%d, pattern=0x%x, flags=0x%lx\n",
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__func__, sg_dma_address(sg), sg_dma_len(sg),
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value, flags);
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desc = at_xdmac_memset_create_desc(chan, atchan,
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sg_dma_address(sg),
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sg_dma_len(sg),
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value);
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if (!desc && first)
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list_splice_init(&first->descs_list,
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&atchan->free_descs_list);
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if (!first)
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first = desc;
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/* Update our strides */
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pstride = stride;
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if (psg)
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stride = sg_dma_address(sg) -
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(sg_dma_address(psg) + sg_dma_len(psg));
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/*
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* The scatterlist API gives us only the address and
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* length of each elements.
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*
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* Unfortunately, we don't have the stride, which we
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* will need to compute.
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*
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* That make us end up in a situation like this one:
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* len stride len stride len
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* +-------+ +-------+ +-------+
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* | N-2 | | N-1 | | N |
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* +-------+ +-------+ +-------+
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*
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* We need all these three elements (N-2, N-1 and N)
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* to actually take the decision on whether we need to
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* queue N-1 or reuse N-2.
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*
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* We will only consider N if it is the last element.
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*/
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if (ppdesc && pdesc) {
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if ((stride == pstride) &&
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(sg_dma_len(ppsg) == sg_dma_len(psg))) {
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dev_dbg(chan2dev(chan),
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"%s: desc 0x%p can be merged with desc 0x%p\n",
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__func__, pdesc, ppdesc);
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/*
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* Increment the block count of the
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* N-2 descriptor
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*/
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at_xdmac_increment_block_count(chan, ppdesc);
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ppdesc->lld.mbr_dus = stride;
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/*
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* Put back the N-1 descriptor in the
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* free descriptor list
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*/
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list_add_tail(&pdesc->desc_node,
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&atchan->free_descs_list);
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/*
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* Make our N-1 descriptor pointer
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* point to the N-2 since they were
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* actually merged.
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*/
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pdesc = ppdesc;
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/*
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* Rule out the case where we don't have
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* pstride computed yet (our second sg
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* element)
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*
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* We also want to catch the case where there
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* would be a negative stride,
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*/
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} else if (pstride ||
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sg_dma_address(sg) < sg_dma_address(psg)) {
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/*
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* Queue the N-1 descriptor after the
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* N-2
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*/
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at_xdmac_queue_desc(chan, ppdesc, pdesc);
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/*
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* Add the N-1 descriptor to the list
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* of the descriptors used for this
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* transfer
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*/
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list_add_tail(&desc->desc_node,
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&first->descs_list);
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dev_dbg(chan2dev(chan),
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"%s: add desc 0x%p to descs_list 0x%p\n",
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__func__, desc, first);
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}
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}
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/*
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* If we are the last element, just see if we have the
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* same size than the previous element.
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*
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* If so, we can merge it with the previous descriptor
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* since we don't care about the stride anymore.
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*/
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if ((i == (sg_len - 1)) &&
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sg_dma_len(ppsg) == sg_dma_len(psg)) {
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dev_dbg(chan2dev(chan),
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"%s: desc 0x%p can be merged with desc 0x%p\n",
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__func__, desc, pdesc);
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/*
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* Increment the block count of the N-1
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* descriptor
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*/
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at_xdmac_increment_block_count(chan, pdesc);
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pdesc->lld.mbr_dus = stride;
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/*
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* Put back the N descriptor in the free
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* descriptor list
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*/
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list_add_tail(&desc->desc_node,
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&atchan->free_descs_list);
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}
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/* Update our descriptors */
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ppdesc = pdesc;
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pdesc = desc;
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/* Update our scatter pointers */
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ppsg = psg;
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psg = sg;
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len += sg_dma_len(sg);
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}
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first->tx_dma_desc.cookie = -EBUSY;
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first->tx_dma_desc.flags = flags;
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first->xfer_size = len;
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return &first->tx_dma_desc;
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}
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static enum dma_status
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at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
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struct dma_tx_state *txstate)
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@ -1736,6 +1895,7 @@ static int at_xdmac_probe(struct platform_device *pdev)
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dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask);
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dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
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dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask);
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dma_cap_set(DMA_MEMSET_SG, atxdmac->dma.cap_mask);
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dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
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/*
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* Without DMA_PRIVATE the driver is not able to allocate more than
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@ -1751,6 +1911,7 @@ static int at_xdmac_probe(struct platform_device *pdev)
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atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved;
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atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
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atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset;
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atxdmac->dma.device_prep_dma_memset_sg = at_xdmac_prep_dma_memset_sg;
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atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
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atxdmac->dma.device_config = at_xdmac_device_config;
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atxdmac->dma.device_pause = at_xdmac_device_pause;
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