arm64/sysreg: Make BHB clear feature defines match the architecture
The architecture refers to the field identifying support for BHB clear as BC but the kernel has called it CLEARBHB. In preparation for generation of defines for ID_AA64ISAR2_EL1 rename to use the architecture's naming. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-11-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
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@ -673,7 +673,7 @@ static inline bool supports_clearbhb(int scope)
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isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
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return cpuid_feature_extract_unsigned_field(isar2,
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ID_AA64ISAR2_CLEARBHB_SHIFT);
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ID_AA64ISAR2_BC_SHIFT);
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}
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const struct cpumask *system_32bit_el0_cpumask(void);
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@ -738,7 +738,7 @@
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#define ID_AA64ISAR1_GPI_IMP 0x1
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/* id_aa64isar2 */
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#define ID_AA64ISAR2_CLEARBHB_SHIFT 28
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#define ID_AA64ISAR2_BC_SHIFT 28
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#define ID_AA64ISAR2_APA3_SHIFT 12
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#define ID_AA64ISAR2_GPA3_SHIFT 8
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#define ID_AA64ISAR2_RPRES_SHIFT 4
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@ -231,7 +231,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
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};
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static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_BC_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
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FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
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