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perf vendor events intel: Update sapphirerapids events to v1.17

Browse Source 
Update to v1.17 released in:

  https://github.com/intel/perfmon/pull/123

Add events FP_ARITH_DISPATCHED.V0, FP_ARITH_DISPATCHED.V1,
FP_ARITH_DISPATCHED.V2, UNC_IIO_IOMMU0.1G_HITS, UNC_IIO_IOMMU0.2M_HITS
and UNC_IIO_IOMMU0.4K_HITS. Description updates.

Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20240104074259.653219-4-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2024-01-03 23:42:59 -08:00 committed by Arnaldo Carvalho de Melo
parent 8550506887
commit 360b045fce
5 changed files with 60 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tools/perf/pmu-events/arch/x86/mapfile.csv
View File

@ -26,7 +26,7 @@ GenuineIntel-6-1[AEF],v4,nehalemep,core
GenuineIntel-6-2E,v4,nehalemex,core
GenuineIntel-6-A7,v1.01,rocketlake,core
GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-8F,v1.16,sapphirerapids,core
GenuineIntel-6-8F,v1.17,sapphirerapids,core
GenuineIntel-6-AF,v1.00,sierraforest,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v57,skylake,core

1 Family-model Version Filename EventType
26 GenuineIntel-6-2E v4 nehalemex core
27 GenuineIntel-6-A7 v1.01 rocketlake core
28 GenuineIntel-6-2A v19 sandybridge core
29 GenuineIntel-6-8F v1.16 v1.17 sapphirerapids core
30 GenuineIntel-6-AF v1.00 sierraforest core
31 GenuineIntel-6-(37|4A|4C|4D|5A) v15 silvermont core
32 GenuineIntel-6-(4E|5E|8E|9E|A5|A6) v57 skylake core

27
tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json
View File

@ -23,26 +23,47 @@
"UMask": "0x10"
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_0",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_1",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_5",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.V0",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.V1",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.V2",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"EventCode": "0xc7",

2
tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json
View File

@ -505,7 +505,7 @@
"UMask": "0x1"
},
{
"BriefDescription": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
"BriefDescription": "Bubble cycles of BAClear (Unknown Branch).",
"EventCode": "0xad",
"EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
"MSRIndex": "0x3F7",

8
tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnect.json
View File

@ -4825,11 +4825,11 @@
"Unit": "M3UPI"
},
{
"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD Bouncable)",
"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD Bounceable)",
"EventCode": "0x47",
"EventName": "UNC_MDF_CRS_TxR_INSERTS.AD_BNC",
"PerPkg": "1",
"PublicDescription": "AD Bouncable : Number of allocations into the CRS Egress",
"PublicDescription": "AD Bounceable : Number of allocations into the CRS Egress",
"UMask": "0x1",
"Unit": "MDF"
},
@ -4861,11 +4861,11 @@
"Unit": "MDF"
},
{
"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL Bouncable)",
"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL Bounceable)",
"EventCode": "0x47",
"EventName": "UNC_MDF_CRS_TxR_INSERTS.BL_BNC",
"PerPkg": "1",
"PublicDescription": "BL Bouncable : Number of allocations into the CRS Egress",
"PublicDescription": "BL Bounceable : Number of allocations into the CRS Egress",
"UMask": "0x4",
"Unit": "MDF"
},

30
tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json
View File

@ -1249,6 +1249,36 @@
"UMask": "0x70ff010",
"Unit": "IIO"
},
{
"BriefDescription": ": IOTLB Hits to a 1G Page",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.1G_HITS",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.",
"UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": ": IOTLB Hits to a 2M Page",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.2M_HITS",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.",
"UMask": "0x8",
"Unit": "IIO"
},
{
"BriefDescription": ": IOTLB Hits to a 4K Page",
"EventCode": "0x40",
"EventName": "UNC_IIO_IOMMU0.4K_HITS",
"PerPkg": "1",
"PortMask": "0x0000",
"PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.",
"UMask": "0x4",
"Unit": "IIO"
},
{
"BriefDescription": ": Context cache hits",
"EventCode": "0x40",