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ata: sata_mv: add proper definitions for LP_PHY_CTL register values

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Commit 9013d64e66 ("ata: sata_mv: fix disk hotplug for Armada
370/XP SoCs") added some manipulation of the LP_PHY_CTL register, but
using magic values. This commit changes the code to use proper
definitions for the LP_PHY_CTL register, which allows to document what
the different bits are doing.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Tejun Heo <tj@kernel.org>
This commit is contained in:
Thomas Petazzoni 2015-03-19 14:36:37 +01:00 committed by Tejun Heo
parent 7b09ac704b
commit 3661aa99d8
1 changed files with 16 additions and 4 deletions
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20
drivers/ata/sata_mv.c
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@ -306,6 +306,11 @@ enum {
MV5_PHY_CTL = 0x0C, MV5_PHY_CTL = 0x0C,
SATA_IFCFG = 0x050, SATA_IFCFG = 0x050,
LP_PHY_CTL = 0x058, LP_PHY_CTL = 0x058,
LP_PHY_CTL_PIN_PU_PLL = (1 << 0),
LP_PHY_CTL_PIN_PU_RX = (1 << 1),
LP_PHY_CTL_PIN_PU_TX = (1 << 2),
LP_PHY_CTL_GEN_TX_3G = (1 << 5),
LP_PHY_CTL_GEN_RX_3G = (1 << 9),
MV_M2_PREAMP_MASK = 0x7e0, MV_M2_PREAMP_MASK = 0x7e0,
@ -1391,10 +1396,17 @@ static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
/* /*
* Set PHY speed according to SControl speed. * Set PHY speed according to SControl speed.
*/ */
if ((val & 0xf0) == 0x10) u32 lp_phy_val =
writelfl(0x7, lp_phy_addr); LP_PHY_CTL_PIN_PU_PLL |
else LP_PHY_CTL_PIN_PU_RX |
writelfl(0x227, lp_phy_addr); LP_PHY_CTL_PIN_PU_TX;
if ((val & 0xf0) != 0x10)
lp_phy_val |=
LP_PHY_CTL_GEN_TX_3G |
LP_PHY_CTL_GEN_RX_3G;
writelfl(lp_phy_val, lp_phy_addr);
} }
} }
writelfl(val, addr); writelfl(val, addr);