MIPS: BMIPS: Explicitly configure reset vectors prior to secondary boot
The secondary CPU's reset vector needs to be set to KSEG1 for a cold boot (release from reset), or KSEG0 for a warm restart. On a cold boot KSEG0 may be unavailable (BMIPS4380), and on a warm restart KSEG1 may be unavailable (XKS01 mode on 4380 or 5000). Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -47,6 +47,8 @@ cpumask_t bmips_booted_mask;
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#define RESET_FROM_KSEG0 0x80080800
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#define RESET_FROM_KSEG1 0xa0080800
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static void bmips_set_reset_vec(int cpu, u32 val);
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#ifdef CONFIG_SMP
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/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
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@ -198,6 +200,9 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
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pr_info("SMP: Booting CPU%d...\n", cpu);
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if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
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/* kseg1 might not exist if this CPU enabled XKS01 */
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bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
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switch (current_cpu_type()) {
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case CPU_BMIPS4350:
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case CPU_BMIPS4380:
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@ -207,8 +212,9 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
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bmips5000_send_ipi_single(cpu, 0);
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break;
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}
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}
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else {
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} else {
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bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
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switch (current_cpu_type()) {
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case CPU_BMIPS4350:
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case CPU_BMIPS4380:
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@ -229,31 +235,12 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
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*/
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static void bmips_init_secondary(void)
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{
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/* move NMI vector to kseg0, in case XKS01 is enabled */
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void __iomem *cbr;
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unsigned long old_vec;
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unsigned long relo_vector;
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int boot_cpu;
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switch (current_cpu_type()) {
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case CPU_BMIPS4350:
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case CPU_BMIPS4380:
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cbr = BMIPS_GET_CBR();
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boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
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relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
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BMIPS_RELO_VECTOR_CONTROL_1;
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old_vec = __raw_readl(cbr + relo_vector);
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__raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
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clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
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break;
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case CPU_BMIPS5000:
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write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
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(smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
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write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
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break;
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}
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