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phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation

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PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-10-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Swapnil Jakhade 2021-12-23 07:01:31 +01:00 committed by Vinod Koul
parent f1cc6c3f08
commit 36ce416330
1 changed files with 72 additions and 1 deletions
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73
drivers/phy/cadence/phy-cadence-sierra.c
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@ -151,6 +151,13 @@
#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0
#define SIERRA_PHY_PLL_CFG 0xe
/* PHY PCS lane registers */
#define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
((0xD000 << (block_offset)) + \
(((ln) << 8) << (reg_offset)))
#define SIERRA_PHY_ISO_LINK_CTRL 0xB
/* PHY PMA common registers */
#define SIERRA_PHY_PMA_COMMON_OFFSET(block_offset) \
(0xE000 << (block_offset))
@ -181,6 +188,8 @@ static const struct reg_field pma_cmn_ready =
REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
static const struct reg_field phy_iso_link_ctrl_1 =
REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1);
static const char * const clk_names[] = {
[CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
@ -287,12 +296,14 @@ struct cdns_sierra_phy {
struct reset_control *apb_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pcs_common_cdb;
struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pma_common_cdb;
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
struct regmap_field *pma_cmn_ready;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES];
struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
@ -367,6 +378,34 @@ static const struct regmap_config cdns_sierra_phy_pcs_cmn_cdb_config = {
.reg_read = cdns_regmap_read,
};
#define SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
{ \
.name = "sierra_phy_pcs_lane" n "_cdb", \
.reg_stride = 1, \
.fast_io = true, \
.reg_write = cdns_regmap_write, \
.reg_read = cdns_regmap_read, \
}
static const struct regmap_config cdns_sierra_phy_pcs_lane_cdb_config[] = {
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("4"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("5"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("6"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("7"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("8"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("9"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("10"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("11"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("12"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("13"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("14"),
SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("15"),
};
static const struct regmap_config cdns_sierra_phy_pma_cmn_cdb_config = {
.name = "sierra_phy_pma_cmn_cdb",
.reg_stride = 1,
@ -452,6 +491,15 @@ static int cdns_sierra_phy_on(struct phy *gphy)
return ret;
}
if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) {
ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane],
val, !val, 1000, PLL_LOCK_TIME);
if (ret) {
dev_err(dev, "Timeout waiting for PHY status ready\n");
return ret;
}
}
/*
* Wait for cmn_ready assertion
* PHY_PMA_CMN_CTRL[0] == 1
@ -755,7 +803,17 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
return PTR_ERR(field);
}
sp->pllctrl_lock[i] = field;
sp->pllctrl_lock[i] = field;
}
for (i = 0; i < SIERRA_MAX_LANES; i++) {
regmap = sp->regmap_phy_pcs_lane_cdb[i];
field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1);
if (IS_ERR(field)) {
dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i);
return PTR_ERR(field);
}
sp->phy_iso_link_ctrl_1[i] = field;
}
return 0;
@ -801,6 +859,19 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
}
sp->regmap_phy_pcs_common_cdb = regmap;
for (i = 0; i < SIERRA_MAX_LANES; i++) {
block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,
reg_offset_shift);
regmap = cdns_regmap_init(dev, base, block_offset,
reg_offset_shift,
&cdns_sierra_phy_pcs_lane_cdb_config[i]);
if (IS_ERR(regmap)) {
dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
return PTR_ERR(regmap);
}
sp->regmap_phy_pcs_lane_cdb[i] = regmap;
}
block_offset = SIERRA_PHY_PMA_COMMON_OFFSET(block_offset_shift);
regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
&cdns_sierra_phy_pma_cmn_cdb_config);